[Bug] 出现大量表格渲染场景时，内存会出现异常大量占用

[lightshing]

📦 部署方式

Other

📌 软件版本

2.15.8

💻 系统环境

macOS

📌 系统版本

15.2

🌐 浏览器

Safari

📌 浏览器版本

18.2

🐛 问题描述

GPT回答给出表格，进行渲染时，会占用大量内存（感觉大概率是表格渲染造成的，下面给出了gpt回答原文

📷 复现步骤

GPT回答如下，屏幕截图如下：

Let's continue clearly from where we stopped and answer the remaining questions step by step:

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4. Latency of beq (branch) instruction:

The beq instruction does the following:

• IF: Instruction fetch (PC read + Instruction Memory read)
• ID: Register read (two registers) and Sign Extension (for branch offset)
• EX: Compare two register values (done by ALU), and calculate branch address (done by an Adder)
• MEM: No data memory access
• WB: No register write-back

Let's carefully identify the critical path for each stage clearly:

Stage	Components	Latency
IF	PC read (94 ps) + Instruction Memory (994 ps)	1088 ps
ID	Register File read (200 ps) + Sign Extension (45 ps, parallel)	200 ps
EX	ALU (for comparison, 150 ps) and Adder (for branch address calculation, 100 ps). These two operations occur in parallel, so we take the longer one.	150 ps
MEM	No memory access, no operation needed	0 ps
WB	No write-back	0 ps

Total Latency (beq) = 1088 + 200 + 150 + 0 + 0 = 1438 ps

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5. Latency of an I-type instruction (e.g., addi):

Typical I-type instructions (like addi) perform:

• IF: Instruction fetch (PC read + Instruction Memory read)
• ID: Register read (one register) + Sign Extension (immediate value)
• EX: ALU operation (register + immediate)
• MEM: No memory access
• WB: Write back ALU result into register file (through MUX and register setup)

Let's carefully identify the critical path for each stage clearly:

Stage	Components	Latency
IF	PC read (94 ps) + Instruction Memory (994 ps)	1088 ps
ID	Register File read (200 ps) + Sign Extension (45 ps, parallel)	200 ps
EX	MUX (25 ps, to select ALU input) + ALU (150 ps)	175 ps
MEM	No memory access, just pass through a MUX (25 ps)	25 ps
WB	MUX (25 ps, select data to write back) + Register setup (50 ps)	75 ps

Total Latency (I-type) = 1088 + 200 + 175 + 25 + 75 = 1563 ps

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✅ Summary of Latencies (All Instructions):

Instruction Type	Latency (ps)
R-type	1538 ps
ld (load)	2532 ps
sd (store)	2457 ps
beq (branch)	1438 ps
I-type (addi)	1563 ps

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6. Minimum Clock Period (Critical Path):

To find the minimum clock period, we must identify the longest single stage among all instructions. The pipeline clock period must accommodate the slowest pipeline stage.

Let's check each stage carefully across all instruction types:

Stage	R-type	ld	sd	beq	I-type	Longest
IF	1088	1088	1088	1088	1088	1088 ps
ID	200	200	200	200	200	200 ps
EX	175	175	175	150	175	175 ps
MEM	25	994	994	0	25	994 ps
WB	50	75	0	0	75	75 ps

Clearly, the longest pipeline stage is the IF stage (1088 ps) and the MEM stage for load/store (994 ps). The IF stage (1088 ps) is the longest and thus determines the minimum clock period.

✅ Minimum Clock Period = 1088 ps

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📝 Final Answers clearly stated:

Question	Answer
2. Latency of ld	2532 ps
3. Latency of sd	2457 ps
4. Latency of beq	1438 ps
5. Latency of I-type	1563 ps
6. Minimum Clock Period	1088 ps

🚦 期望结果

No response

📝 补充信息

No response

[Issues-translate-bot]

Bot detected the issue body's language is not English, translate it automatically.

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Title: [Bug] When a large number of table rendering scenes occur, the memory will be consumed very much.

[lightshing]

Cannot seem to reproduce the problem