[SROA] Check typeSizeEqualsStoreSize in isVectorPromotionViable

Commit de3445e (https://reviews.llvm.org/D132096) made
changes to isVectorPromotionViable basically doing

  // Create Vector with size of V, and each element of type Ty
  ...
  uint64_t ElementSize = DL.getTypeStoreSizeInBits(Ty).getFixedSize();
  uint64_t VectorSize = DL.getTypeSizeInBits(V).getFixedSize();
  ...
  VectorType *VTy = VectorType::get(Ty, VectorSize / ElementSize, false);

Not quite sure why it uses the TypeStoreSize for the ElementSize,
but the new vector would only match in size with the old vector in
situations when the TypeStoreSize equals the TypeSize for Ty.
Therefore this patch adds a typeSizeEqualsStoreSize check as yet
another condition for allowing the the new type as a promotion
candidate.

Without this fix the new @test15 test would fail with an assert
like this:

opt: ../lib/Transforms/Scalar/SROA.cpp:1966:
  auto isVectorPromotionViable(llvm::sroa::Partition &,
                               const llvm::DataLayout &)
       ::(anonymous class)::operator()(llvm::VectorType *,
                                       llvm::VectorType *) const:
  Assertion `DL.getTypeSizeInBits(RHSTy).getFixedSize() ==
             DL.getTypeSizeInBits(LHSTy).getFixedSize() &&
             "Cannot have vector types of different sizes!"' failed.
 ...
 #8  isVectorPromotionViable(...)::$_10::operator()...
 #9  llvm::SROAPass::rewritePartition(...)
#10  llvm::SROAPass::splitAlloca(...)
#11  llvm::SROAPass::runOnAlloca(...)
#12  llvm::SROAPass::runImpl(...)
#13  llvm::SROAPass::run(...)

Reviewed By: MatzeB

Differential Revision: https://reviews.llvm.org/D134032

Author: bjope

llvm/lib/Transforms/Scalar/SROA.cpp

@@ -1933,6 +1933,8 @@ static VectorType *isVectorPromotionViable(Partition &P, const DataLayout &DL) {
       continue;
     if (isa<VectorType>(Ty))
       continue;
+    if (!DL.typeSizeEqualsStoreSize(Ty))
+      continue;
     // Create Vector with size of V, and each element of type Ty
     VectorType *V = CandidateTys[0];
     uint64_t ElementSize = DL.getTypeStoreSizeInBits(Ty).getFixedSize();

llvm/test/Transforms/SROA/vector-promotion.ll

@@ -628,3 +628,19 @@ entry:
   %add2 = add i32 %add, %add1
   ret i32 %add2
 }
+
+; This used to hit an assert after commit de3445e0ef15c4.
+; Added as regression test to verify that we handle this without crashing.
+define i1 @test15() {
+; CHECK-LABEL: @test15(
+; CHECK-NEXT:    [[A_SROA_0:%.*]] = alloca <2 x i64>, align 32
+; CHECK-NEXT:    store <2 x i64> <i64 0, i64 -1>, ptr [[A_SROA_0]], align 32
+; CHECK-NEXT:    [[A_SROA_0_0_A_SROA_0_0_L:%.*]] = load i1, ptr [[A_SROA_0]], align 32
+; CHECK-NEXT:    ret i1 [[A_SROA_0_0_A_SROA_0_0_L]]
+;
+  %a = alloca <8 x i32>
+  store <2 x i64> <i64 0, i64 -1>, ptr %a
+  %l = load i1, ptr %a, align 1
+  ret i1 %l
+
+}