command-“stat”information

[fwj0610]

hello，my command is follow：
read_verilog /home/desktop/yosys/yosys/tests/simple/hierarchy.v
techmap; opt
abc -lut 4
tee -o log-0727 stat
in log-0727 file,i want to know explanation of "wires、wire bits、public wires、public wire bits 、memories 、memory bits、processes、cells”,donot find information in yosys_manual;thanks.

[nakengelhardt]

I'm not sure what kind of information you are looking for? This is giving you the number of each of these elements that is contained in the design at the current state of synthesis. The manual explains the RTLIL elements Wire Cell Memory and Process in Chapter 4, as well as what is public vs. private Wire in 4.2.1. The ___ bits entries are adding up the sizes of all the elements, which allows comparison between coarse grain (where entire buses are a single element) and fine grain (where each bit is its own element).