making lut to provide constant 0

[narutozxp]

I had written a mapping file making lut to provide a constant 0. Its contents are as follows.

        \$lut #(
            .WIDTH(3),
            .LUT(8'b00000000)
        ) lut3_zero0 (
            .A(),
            .Y(zero0)
        );

In such case, the inputs of lut is unconnected, as its Truth Table is 8'b00000000. However, it raised an error.

ERROR: Found error in internal cell \adder_bench.$add$./benchmark/adder_bench.v:42$4.genblk1.genblk1.genblk1.tail.lut3_zero3 ($lut) at kernel/rtlil.cc:1077:
  attribute \module_not_derived 1
  attribute \src "./benchmark/adder_bench.v:42.17-42.34|/home/data/shawn/eFPGA/Code/zxp/eFPGA/OpenFPGA/GW1N4/Yosys/k4n8_adder_map.v:112.11-115.10"
  cell $lut $add$./benchmark/adder_bench.v:42$4.genblk1.genblk1.genblk1.tail.lut3_zero3
    parameter \LUT 8'00000000
    parameter signed \WIDTH 3
    connect \Y $add$./benchmark/adder_bench.v:42$4.genblk1.genblk1.genblk1.zero3
    connect \A { }
  end

Is there any way to solve such problems?

[povik]

No matter the thruth table you need to connect a 3 bit wide signal on the input port (as for any $lut with WIDTH set to 3), so you could do

        \$lut #(
            .WIDTH(3),
            .LUT(8'b00000000)
        ) lut3_zero0 (
            .A(3'b000),
            .Y(zero0)
        );

but maybe what you are looking for is

    assign zero0 = 1'b0;

That depends on what you are trying to achieve with the mapping file.

[narutozxp]

Yosys defines a single variable, $false, representing the boolean value False (logic 0). However, I would like to have multiple variables like $false. I have no idea how to reach my goal.