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AHB seems to be working
Signed-off-by: Anderson Ignacio da Silva <[email protected]>
1 parent ea33b4e commit 419e181

38 files changed

+8286
-205
lines changed

.DS_Store

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ahb_template.gtkw

+128
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,128 @@
1+
[*]
2+
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
3+
[*] Tue May 21 22:13:34 2024
4+
[*]
5+
[dumpfile] "nox_waves.fst"
6+
[dumpfile_mtime] "Tue May 21 22:05:46 2024"
7+
[dumpfile_size] 3059157
8+
[savefile] "ahb_template.gtkw"
9+
[timestart] 182791
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[size] 2384 1412
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[pos] 2005 426
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*-6.047431 182560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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[markername] AA
14+
[markername] BB
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[markername] CC
16+
[markername] DD
17+
[markername] EE
18+
[markername] FF
19+
[markername] GG
20+
[markername] HH
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[markername] II
22+
[markername] JJ
23+
[markername] KK
24+
[markername] LL
25+
[markername] MM
26+
[markername] NN
27+
[markername] OO
28+
[markername] PP
29+
[markername] QQ
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[markername] RR
31+
[markername] SS
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[markername] TT
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[markername] UU
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[markername] VV
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[markername] WW
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[markername] XX
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[markername] YY
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[markername] ZZ
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[treeopen] TOP.
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[treeopen] TOP.nox_soc.
41+
[treeopen] TOP.nox_soc.u_nox_wrapper.
42+
[treeopen] TOP.nox_soc.u_nox_wrapper.u_nox.
43+
[treeopen] TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.
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[sst_width] 362
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[signals_width] 296
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[sst_expanded] 1
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[sst_vpaned_height] 611
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@28
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TOP.nox_soc.rst
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TOP.nox_soc.clk
51+
@200
52+
-
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@10023
54+
TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.haddr[31:0]
55+
@800200
56+
-instr_nox
57+
@28
58+
TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.hready
59+
@22
60+
TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.haddr[31:0]
61+
@28
62+
TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.hsel
63+
@100000028
64+
TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.hsize[2:0]
65+
TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.htrans[1:0]
66+
@22
67+
TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.hwdata[31:0]
68+
@28
69+
TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.hwrite
70+
@200
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-
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@28
73+
TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_miso.hready
74+
TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_miso.hresp
75+
@22
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TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_miso.hrdata[31:0]
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@1000200
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-instr_nox
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@c00200
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-lsu_nox
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@28
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TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.hready
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@22
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TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.haddr[31:0]
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@28
86+
TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.hsel
87+
@100000028
88+
TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.hsize[2:0]
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TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.htrans[1:0]
90+
@22
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TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.hwdata[31:0]
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@28
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TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.hwrite
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@200
95+
-
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@28
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TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_miso.hready
98+
TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_miso.hresp
99+
@22
100+
TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_miso.hrdata[31:0]
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@1401200
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-lsu_nox
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@28
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TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.fetch_req_i
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@22
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TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.fetch_addr_i[31:0]
107+
@28
108+
TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.next_req
109+
@100000028
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TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.st_ff[1:0]
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@28
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TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.jump
113+
TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.req_ff
114+
TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.dp_ff
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@200
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-
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@28
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TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.fetch_valid_o
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@22
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TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.fetch_instr_o[31:0]
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@28
122+
TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.fetch_ready_i
123+
@24
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TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.buffer_space[1:0]
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@420
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TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.L0_BUFFER_SIZE
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[pattern_trace] 1
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[pattern_trace] 0

bus_arch_sv_pkg

makefile

+15-8
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
AXI_IF ?= 1
1+
AXI_IF ?= 0
22
GTKWAVE_PRE := /Applications/gtkwave.app/Contents/Resources/bin/
33
# Design files
44
_SRC_VERILOG ?= bus_arch_sv_pkg/amba_axi_pkg.sv
@@ -42,7 +42,13 @@ _SOC_VERILOG += xlnx/rtl/nox_wrapper.sv
4242
_SOC_VERILOG += xlnx/rtl/cdc_async_fifo.sv
4343
_SOC_VERILOG += xlnx/rtl/axi_spi_master.sv
4444
_SOC_VERILOG += xlnx/rtl/axi_mtimer.sv
45+
_SOC_VERILOG += xlnx/rtl/ahb_mem.sv
46+
_SOC_VERILOG += xlnx/rtl/cmsdk_ahb_to_sram.v
47+
_SOC_VERILOG += xlnx/rtl/cmsdk_fpga_sram.v
48+
_SOC_VERILOG += xlnx/rtl/nox_ahb_ram.sv
4549
_SOC_VERILOG += sw/bootloader/output/boot_rom.sv
50+
_SOC_VERILOG += $(shell find xlnx/rtl/ahb_interconnect -type f -iname *.v)
51+
_SOC_VERILOG += $(shell find xlnx/rtl/ahb_interconnect -type f -iname *.sv)
4652

4753
ifeq ($(AXI_IF),0)
4854
_SOC_VERILOG += xlnx/rtl/nox_soc_ahb.sv
@@ -59,12 +65,12 @@ INCS_VLOG := $(addprefix -I,$(_INCS_VLOG))
5965
#IRAM_KB_SIZE ?= 2*1024 #2MB due to J-Tests on RV Compliance tests
6066
IRAM_KB_SIZE ?= 128
6167
DRAM_KB_SIZE ?= 32
62-
ENTRY_ADDR ?= \'h8000_0000
63-
IRAM_ADDR ?= 0x80000000
64-
DRAM_ADDR ?= 0x10000000
68+
ENTRY_ADDR ?= \'h0000_0000
69+
IRAM_ADDR ?= 0x00000000
70+
DRAM_ADDR ?= 0x00020000
6571
# For NoX SoC
66-
IRAM_ADDR_SOC ?= 0xa0000000
67-
DRAM_ADDR_SOC ?= 0x10000000
72+
IRAM_ADDR_SOC ?= 0x00000000
73+
DRAM_ADDR_SOC ?= 0x00020000
6874
DISPLAY_TEST ?= 0 # Enable $display in axi_mem.sv [compliance test]
6975
WAVEFORM_USE ?= 1 # Use 0 to not generate waves [compliance test]
7076

@@ -120,7 +126,8 @@ RUN_CMD_COMP := docker run --rm --name ship_nox \
120126

121127
RUN_SW := sw/hello_world/output/hello_world.elf
122128
#RUN_SW_SOC := sw/bootloader/output/bootloader.elf
123-
RUN_SW_SOC := sw/soc_hello_world/output/soc_hello_world.elf
129+
#RUN_SW_SOC := sw/soc_hello_world/output/soc_hello_world.elf
130+
RUN_SW_SOC := sw/hello_world/output/hello_world.elf
124131
#RUN_SW_SOC := sw/FreeRTOS_demo/output/FreeRTOS_demo.elf
125132

126133
CPPFLAGS_VERI := "$(INCS_CPP) -O0 -g3 -Wall \
@@ -244,7 +251,7 @@ soc: clean $(VERI_EXE_SOC)
244251
@echo "\n"
245252

246253
$(RUN_SW_SOC):
247-
make -C sw/soc_hello_world all UART_MODE=UART_SIM
254+
make -C sw/hello_world all UART_MODE=UART_SIM
248255

249256
run_soc: $(RUN_SW_SOC)
250257
$(RUN_CMD) ./$(VERI_EXE_SOC) -s 100000 -e $<

rtl/cb_to_ahb.sv

+41-4
Original file line numberDiff line numberDiff line change
@@ -3,20 +3,36 @@
33
* License : MIT license <Check LICENSE>
44
* Author : Anderson Ignacio da Silva (aignacio) <[email protected]>
55
* Date : 23.10.2021
6-
* Last Modified Date: 25.02.2022
6+
* Last Modified Date: 15.05.2024
77
*/
88
module cb_to_ahb
99
import amba_axi_pkg::*;
1010
import amba_ahb_pkg::*;
1111
import nox_utils_pkg::*;
1212
(
13+
input clk,
14+
input rst,
1315
// Core bus Master I/F
1416
input s_cb_mosi_t cb_mosi_i,
1517
output s_cb_miso_t cb_miso_o,
1618
// AXI Master I/F
1719
output s_ahb_mosi_t ahb_mosi_o,
1820
input s_ahb_miso_t ahb_miso_i
1921
);
22+
logic req_rd_ff, next_rd_req;
23+
logic req_wr_ff, next_wr_req;
24+
25+
`CLK_PROC(clk, rst) begin
26+
`RST_TYPE(rst) begin
27+
req_rd_ff <= 1'b0;
28+
req_wr_ff <= '0;
29+
end
30+
else begin
31+
req_rd_ff <= next_rd_req;
32+
req_wr_ff <= next_wr_req;
33+
end
34+
end
35+
2036
always_comb begin
2137
ahb_mosi_o = s_ahb_mosi_t'('0);
2238
cb_miso_o = s_cb_miso_t'('0);
@@ -33,15 +49,36 @@ module cb_to_ahb
3349
end
3450
ahb_mosi_o.hwdata = cb_mosi_i.wr_data_valid ? cb_mosi_i.wr_data : 'h0;
3551

52+
next_rd_req = req_rd_ff;
53+
next_wr_req = req_wr_ff;
54+
55+
if (req_rd_ff && ahb_miso_i.hready) begin
56+
next_rd_req = 1'b0;
57+
end
58+
59+
if (req_wr_ff && ahb_miso_i.hready) begin
60+
next_wr_req = 1'b0;
61+
end
62+
63+
64+
if (ahb_mosi_o.hsel && (ahb_mosi_o.htrans != AHB_IDLE) && ahb_miso_i.hready) begin
65+
if (ahb_mosi_o.hwrite) begin
66+
next_wr_req = 1'b1;
67+
end
68+
else begin
69+
next_rd_req = 1'b1;
70+
end
71+
end
72+
3673
// MISO
3774
cb_miso_o.wr_addr_ready = ahb_miso_i.hready;
38-
cb_miso_o.wr_data_ready = ahb_miso_i.hready;
75+
cb_miso_o.wr_data_ready = ahb_miso_i.hready && req_wr_ff;
3976
cb_miso_o.wr_resp_error = cb_error_t'(ahb_miso_i.hresp);
40-
cb_miso_o.wr_resp_valid = 'b1;
77+
cb_miso_o.wr_resp_valid = ahb_miso_i.hready;
4178
cb_miso_o.rd_addr_ready = ahb_miso_i.hready;
4279
cb_miso_o.rd_data = ahb_miso_i.hrdata;
4380
cb_miso_o.rd_resp = cb_error_t'(ahb_miso_i.hresp);
44-
cb_miso_o.rd_valid = ~ahb_miso_i.hready;
81+
cb_miso_o.rd_valid = ahb_miso_i.hready && req_rd_ff;
4582
end
4683

4784
endmodule

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