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tannergoodingSingleAccretionechesakov
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Expose cross-platform helpers for Vector64, Vector128, and Vector256 (#53450)
* Refactoring Vector<T> to be alphabetically ordered and reduce duplicated code * Adding a debug view to System.Numerics.Vector<T> * Do some basic code cleanup and refactoring of Vector64/128/256 * Updating Vector64/128/256 to expose cross platform helper methods * Adding templated tests for Vector64 * Regenerating templated tests for Vector64 * Adding templated tests for Vector128 * Regenerating templated tests for Vector128 * Adding templated tests for Vector256 * Regenerating templated tests for Vector256 * Fix getSIMDStructFromField to account for accessing the private ulong fields for Vector64/128/256<T> * Ensure helper intrinsics don't insert on importation * Minor cleanup of impBaseIntrinsic for x86/x64 * Intrinsify the Vector64/128/256 methods * Make the internal helper named IsTypeSupported to not conflict with mono's existing check * Ensure we lie about the type for TYP_SIMD32 bitwise ops when only AVX is supported * Use gtNewSimdZeroNode rather than gtNewSIMDVectorZero * Applying formatting patch * Apply suggestions from code review Co-authored-by: SingleAccretion <[email protected]> * Apply suggestions from code review * Split HardwareIntrinsic tests into 3 groups * Update src/coreclr/vm/class.cpp Co-authored-by: Egor Chesakov <[email protected]> Co-authored-by: SingleAccretion <[email protected]> Co-authored-by: Egor Chesakov <[email protected]>
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‎src/coreclr/jit/compiler.h

+145-53
Original file line numberDiff line numberDiff line change
@@ -3123,65 +3123,53 @@ class Compiler
31233123
GenTreeHWIntrinsic* gtNewSimdHWIntrinsicNode(var_types type,
31243124
NamedIntrinsic hwIntrinsicID,
31253125
CorInfoType simdBaseJitType,
3126-
unsigned simdSize);
3127-
GenTreeHWIntrinsic* gtNewSimdHWIntrinsicNode(
3128-
var_types type, GenTree* op1, NamedIntrinsic hwIntrinsicID, CorInfoType simdBaseJitType, unsigned simdSize);
3126+
unsigned simdSize,
3127+
bool isSimdAsHWIntrinsic = false);
3128+
GenTreeHWIntrinsic* gtNewSimdHWIntrinsicNode(var_types type,
3129+
GenTree* op1,
3130+
NamedIntrinsic hwIntrinsicID,
3131+
CorInfoType simdBaseJitType,
3132+
unsigned simdSize,
3133+
bool isSimdAsHWIntrinsic = false);
31293134
GenTreeHWIntrinsic* gtNewSimdHWIntrinsicNode(var_types type,
31303135
GenTree* op1,
31313136
GenTree* op2,
31323137
NamedIntrinsic hwIntrinsicID,
31333138
CorInfoType simdBaseJitType,
3134-
unsigned simdSize);
3139+
unsigned simdSize,
3140+
bool isSimdAsHWIntrinsic = false);
31353141
GenTreeHWIntrinsic* gtNewSimdHWIntrinsicNode(var_types type,
31363142
GenTree* op1,
31373143
GenTree* op2,
31383144
GenTree* op3,
31393145
NamedIntrinsic hwIntrinsicID,
31403146
CorInfoType simdBaseJitType,
3141-
unsigned simdSize);
3147+
unsigned simdSize,
3148+
bool isSimdAsHWIntrinsic = false);
31423149
GenTreeHWIntrinsic* gtNewSimdHWIntrinsicNode(var_types type,
31433150
GenTree* op1,
31443151
GenTree* op2,
31453152
GenTree* op3,
31463153
GenTree* op4,
31473154
NamedIntrinsic hwIntrinsicID,
31483155
CorInfoType simdBaseJitType,
3149-
unsigned simdSize);
3150-
3151-
GenTreeHWIntrinsic* gtNewSimdCreateBroadcastNode(
3152-
var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize, bool isSimdAsHWIntrinsic);
3153-
3154-
GenTreeHWIntrinsic* gtNewSimdGetElementNode(var_types type,
3155-
GenTree* op1,
3156-
GenTree* op2,
3157-
CorInfoType simdBaseJitType,
3158-
unsigned simdSize,
3159-
bool isSimdAsHWIntrinsic);
3160-
3161-
GenTreeHWIntrinsic* gtNewSimdWithElementNode(var_types type,
3162-
GenTree* op1,
3163-
GenTree* op2,
3164-
GenTree* op3,
3165-
CorInfoType simdBaseJitType,
3166-
unsigned simdSize,
3167-
bool isSimdAsHWIntrinsic);
3156+
unsigned simdSize,
3157+
bool isSimdAsHWIntrinsic = false);
31683158

31693159
GenTreeHWIntrinsic* gtNewSimdAsHWIntrinsicNode(var_types type,
31703160
NamedIntrinsic hwIntrinsicID,
31713161
CorInfoType simdBaseJitType,
31723162
unsigned simdSize)
31733163
{
3174-
GenTreeHWIntrinsic* node = gtNewSimdHWIntrinsicNode(type, hwIntrinsicID, simdBaseJitType, simdSize);
3175-
node->gtFlags |= GTF_SIMDASHW_OP;
3176-
return node;
3164+
bool isSimdAsHWIntrinsic = true;
3165+
return gtNewSimdHWIntrinsicNode(type, hwIntrinsicID, simdBaseJitType, simdSize, isSimdAsHWIntrinsic);
31773166
}
31783167

31793168
GenTreeHWIntrinsic* gtNewSimdAsHWIntrinsicNode(
31803169
var_types type, GenTree* op1, NamedIntrinsic hwIntrinsicID, CorInfoType simdBaseJitType, unsigned simdSize)
31813170
{
3182-
GenTreeHWIntrinsic* node = gtNewSimdHWIntrinsicNode(type, op1, hwIntrinsicID, simdBaseJitType, simdSize);
3183-
node->gtFlags |= GTF_SIMDASHW_OP;
3184-
return node;
3171+
bool isSimdAsHWIntrinsic = true;
3172+
return gtNewSimdHWIntrinsicNode(type, op1, hwIntrinsicID, simdBaseJitType, simdSize, isSimdAsHWIntrinsic);
31853173
}
31863174

31873175
GenTreeHWIntrinsic* gtNewSimdAsHWIntrinsicNode(var_types type,
@@ -3191,9 +3179,8 @@ class Compiler
31913179
CorInfoType simdBaseJitType,
31923180
unsigned simdSize)
31933181
{
3194-
GenTreeHWIntrinsic* node = gtNewSimdHWIntrinsicNode(type, op1, op2, hwIntrinsicID, simdBaseJitType, simdSize);
3195-
node->gtFlags |= GTF_SIMDASHW_OP;
3196-
return node;
3182+
bool isSimdAsHWIntrinsic = true;
3183+
return gtNewSimdHWIntrinsicNode(type, op1, op2, hwIntrinsicID, simdBaseJitType, simdSize, isSimdAsHWIntrinsic);
31973184
}
31983185

31993186
GenTreeHWIntrinsic* gtNewSimdAsHWIntrinsicNode(var_types type,
@@ -3204,12 +3191,114 @@ class Compiler
32043191
CorInfoType simdBaseJitType,
32053192
unsigned simdSize)
32063193
{
3207-
GenTreeHWIntrinsic* node =
3208-
gtNewSimdHWIntrinsicNode(type, op1, op2, op3, hwIntrinsicID, simdBaseJitType, simdSize);
3209-
node->gtFlags |= GTF_SIMDASHW_OP;
3210-
return node;
3194+
bool isSimdAsHWIntrinsic = true;
3195+
return gtNewSimdHWIntrinsicNode(type, op1, op2, op3, hwIntrinsicID, simdBaseJitType, simdSize,
3196+
isSimdAsHWIntrinsic);
32113197
}
32123198

3199+
GenTree* gtNewSimdAbsNode(
3200+
var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize, bool isSimdAsHWIntrinsic);
3201+
3202+
GenTree* gtNewSimdBinOpNode(genTreeOps op,
3203+
var_types type,
3204+
GenTree* op1,
3205+
GenTree* op2,
3206+
CorInfoType simdBaseJitType,
3207+
unsigned simdSize,
3208+
bool isSimdAsHWIntrinsic);
3209+
3210+
GenTree* gtNewSimdCeilNode(
3211+
var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize, bool isSimdAsHWIntrinsic);
3212+
3213+
GenTree* gtNewSimdCmpOpNode(genTreeOps op,
3214+
var_types type,
3215+
GenTree* op1,
3216+
GenTree* op2,
3217+
CorInfoType simdBaseJitType,
3218+
unsigned simdSize,
3219+
bool isSimdAsHWIntrinsic);
3220+
3221+
GenTree* gtNewSimdCmpOpAllNode(genTreeOps op,
3222+
var_types type,
3223+
GenTree* op1,
3224+
GenTree* op2,
3225+
CorInfoType simdBaseJitType,
3226+
unsigned simdSize,
3227+
bool isSimdAsHWIntrinsic);
3228+
3229+
GenTree* gtNewSimdCmpOpAnyNode(genTreeOps op,
3230+
var_types type,
3231+
GenTree* op1,
3232+
GenTree* op2,
3233+
CorInfoType simdBaseJitType,
3234+
unsigned simdSize,
3235+
bool isSimdAsHWIntrinsic);
3236+
3237+
GenTree* gtNewSimdCndSelNode(var_types type,
3238+
GenTree* op1,
3239+
GenTree* op2,
3240+
GenTree* op3,
3241+
CorInfoType simdBaseJitType,
3242+
unsigned simdSize,
3243+
bool isSimdAsHWIntrinsic);
3244+
3245+
GenTree* gtNewSimdCreateBroadcastNode(
3246+
var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize, bool isSimdAsHWIntrinsic);
3247+
3248+
GenTree* gtNewSimdDotProdNode(var_types type,
3249+
GenTree* op1,
3250+
GenTree* op2,
3251+
CorInfoType simdBaseJitType,
3252+
unsigned simdSize,
3253+
bool isSimdAsHWIntrinsic);
3254+
3255+
GenTree* gtNewSimdFloorNode(
3256+
var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize, bool isSimdAsHWIntrinsic);
3257+
3258+
GenTree* gtNewSimdGetElementNode(var_types type,
3259+
GenTree* op1,
3260+
GenTree* op2,
3261+
CorInfoType simdBaseJitType,
3262+
unsigned simdSize,
3263+
bool isSimdAsHWIntrinsic);
3264+
3265+
GenTree* gtNewSimdMaxNode(var_types type,
3266+
GenTree* op1,
3267+
GenTree* op2,
3268+
CorInfoType simdBaseJitType,
3269+
unsigned simdSize,
3270+
bool isSimdAsHWIntrinsic);
3271+
3272+
GenTree* gtNewSimdMinNode(var_types type,
3273+
GenTree* op1,
3274+
GenTree* op2,
3275+
CorInfoType simdBaseJitType,
3276+
unsigned simdSize,
3277+
bool isSimdAsHWIntrinsic);
3278+
3279+
GenTree* gtNewSimdSqrtNode(
3280+
var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize, bool isSimdAsHWIntrinsic);
3281+
3282+
GenTree* gtNewSimdUnOpNode(genTreeOps op,
3283+
var_types type,
3284+
GenTree* op1,
3285+
CorInfoType simdBaseJitType,
3286+
unsigned simdSize,
3287+
bool isSimdAsHWIntrinsic);
3288+
3289+
GenTree* gtNewSimdWithElementNode(var_types type,
3290+
GenTree* op1,
3291+
GenTree* op2,
3292+
GenTree* op3,
3293+
CorInfoType simdBaseJitType,
3294+
unsigned simdSize,
3295+
bool isSimdAsHWIntrinsic);
3296+
3297+
GenTree* gtNewSimdZeroNode(var_types type,
3298+
CorInfoType simdBaseJitType,
3299+
unsigned simdSize,
3300+
bool isSimdAsHWIntrinsic);
3301+
32133302
GenTreeHWIntrinsic* gtNewScalarHWIntrinsicNode(var_types type, GenTree* op1, NamedIntrinsic hwIntrinsicID);
32143303
GenTreeHWIntrinsic* gtNewScalarHWIntrinsicNode(var_types type,
32153304
GenTree* op1,
@@ -4317,14 +4406,6 @@ class Compiler
43174406
unsigned simdSize,
43184407
GenTree* newobjThis);
43194408

4320-
GenTree* impSimdAsHWIntrinsicCndSel(CORINFO_CLASS_HANDLE clsHnd,
4321-
var_types retType,
4322-
CorInfoType simdBaseJitType,
4323-
unsigned simdSize,
4324-
GenTree* op1,
4325-
GenTree* op2,
4326-
GenTree* op3);
4327-
43284409
GenTree* impSpecialIntrinsic(NamedIntrinsic intrinsic,
43294410
CORINFO_CLASS_HANDLE clsHnd,
43304411
CORINFO_METHOD_HANDLE method,
@@ -4354,14 +4435,6 @@ class Compiler
43544435
GenTree* impSSE2Intrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
43554436
GenTree* impAvxOrAvx2Intrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
43564437
GenTree* impBMI1OrBMI2Intrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
4357-
4358-
GenTree* impSimdAsHWIntrinsicRelOp(NamedIntrinsic intrinsic,
4359-
CORINFO_CLASS_HANDLE clsHnd,
4360-
var_types retType,
4361-
CorInfoType simdBaseJitType,
4362-
unsigned simdSize,
4363-
GenTree* op1,
4364-
GenTree* op2);
43654438
#endif // TARGET_XARCH
43664439
#endif // FEATURE_HW_INTRINSICS
43674440
GenTree* impArrayAccessIntrinsic(CORINFO_CLASS_HANDLE clsHnd,
@@ -8550,6 +8623,25 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
85508623
#endif
85518624
}
85528625

8626+
#if defined(DEBUG)
8627+
bool IsBaselineSimdIsaSupportedDebugOnly()
8628+
{
8629+
#ifdef FEATURE_SIMD
8630+
#if defined(TARGET_XARCH)
8631+
CORINFO_InstructionSet minimumIsa = InstructionSet_SSE2;
8632+
#elif defined(TARGET_ARM64)
8633+
CORINFO_InstructionSet minimumIsa = InstructionSet_AdvSimd;
8634+
#else
8635+
#error Unsupported platform
8636+
#endif // !TARGET_XARCH && !TARGET_ARM64
8637+
8638+
return compIsaSupportedDebugOnly(minimumIsa) && JitConfig.EnableHWIntrinsic();
8639+
#else
8640+
return false;
8641+
#endif // FEATURE_SIMD
8642+
}
8643+
#endif // DEBUG
8644+
85538645
// Get highest available level for SIMD codegen
85548646
SIMDLevel getSIMDSupportLevel()
85558647
{

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