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Fix mprven bit in DCSR #343

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halfdan-dolva opened this issue Nov 22, 2022 · 5 comments
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Fix mprven bit in DCSR #343

halfdan-dolva opened this issue Nov 22, 2022 · 5 comments
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@silabs-oysteink
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Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Status:Resolved Issue has been resolved, but closure is pending on git merge and/or issuer confirmation Type:Task For any task except bug fixes

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@halfdan-dolva
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The mprven bit is documented as hardwired to 1 while it is hardwired to 0 in the RTL.
@halfdan-dolva
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Also the stopcount bit in the same register is seems to not be implemented

@silabs-oivind silabs-oivind mentioned this issue Dec 8, 2022
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@Silabs-ArjanB
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Should be fixed once merged from 40X to 40S.

@Silabs-ArjanB Silabs-ArjanB added Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Status:Resolved Issue has been resolved, but closure is pending on git merge and/or issuer confirmation Type:Bug For bugs in any content (RTL, Documentation, etc.) Type:Task For any task except bug fixes and removed Type:Bug For bugs in any content (RTL, Documentation, etc.) labels Dec 8, 2022
@silabs-oivind
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@Silabs-ArjanB this is merged to E40S, ticket can be closed.

@Silabs-ArjanB
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@silabs-halfdan Please close this issue if you agree it has been solved.

@halfdan-dolva
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This issue is solved, closing ticket. Also creating new ticket for ISS mismatch for the DCSR cause field.

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@silabs-oysteink silabs-oysteink

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Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Status:Resolved Issue has been resolved, but closure is pending on git merge and/or issuer confirmation Type:Task For any task except bug fixes
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@Silabs-ArjanB @silabs-oivind @silabs-oysteink @halfdan-dolva