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Silabs-ArjanBSilabs-ArjanB
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Merge pull request #784 from silabs-oysteink/silabs-oysteink_debug-param
DEBUG parameter
2 parents 1221171 + e9508a7 commit a58bf24

17 files changed

+616
-470
lines changed

‎bhv/cv32e40x_rvfi.sv

+2-1
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,8 @@ module cv32e40x_rvfi
2222
import cv32e40x_pkg::*;
2323
import cv32e40x_rvfi_pkg::*;
2424
#(
25-
parameter bit SMCLIC = 0
25+
parameter bit SMCLIC = 0,
26+
parameter int DEBUG = 1
2627
)
2728
(
2829
input logic clk_i,

‎bhv/cv32e40x_wrapper.sv

+14-5
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,7 @@ module cv32e40x_wrapper
7171
parameter int PMA_NUM_REGIONS = 0,
7272
parameter pma_cfg_t PMA_CFG[PMA_NUM_REGIONS-1:0] = '{default:PMA_R_DEFAULT},
7373
parameter bit CORE_LOG_ENABLE = 1,
74+
parameter int DEBUG = 1,
7475
parameter logic [31:0] DM_REGION_START = 32'hF0000000,
7576
parameter logic [31:0] DM_REGION_END = 32'hF0003FFF
7677
)
@@ -191,7 +192,7 @@ module cv32e40x_wrapper
191192
);
192193

193194
bind cv32e40x_wb_stage:
194-
core_i.wb_stage_i cv32e40x_wb_stage_sva wb_stage_sva
195+
core_i.wb_stage_i cv32e40x_wb_stage_sva #(.DEBUG(DEBUG)) wb_stage_sva
195196
(
196197
.*
197198
);
@@ -223,6 +224,7 @@ module cv32e40x_wrapper
223224
core_i.controller_i.controller_fsm_i
224225
cv32e40x_controller_fsm_sva
225226
#(.X_EXT(X_EXT),
227+
.DEBUG(DEBUG),
226228
.SMCLIC(SMCLIC))
227229
controller_fsm_sva (
228230
.lsu_outstanding_cnt (core_i.load_store_unit_i.cnt_q),
@@ -246,14 +248,15 @@ module cv32e40x_wrapper
246248
bind cv32e40x_cs_registers:
247249
core_i.cs_registers_i
248250
cv32e40x_cs_registers_sva
249-
#(.SMCLIC(SMCLIC))
251+
#(.SMCLIC(SMCLIC),
252+
.DEBUG (DEBUG))
250253
cs_registers_sva (.wb_valid_i (core_i.wb_valid ),
251254
.ctrl_fsm_cs (core_i.controller_i.controller_fsm_i.ctrl_fsm_cs),
252255
.*);
253256

254257

255258
bind cv32e40x_load_store_unit:
256-
core_i.load_store_unit_i cv32e40x_load_store_unit_sva #(.DEPTH (DEPTH)) load_store_unit_sva (
259+
core_i.load_store_unit_i cv32e40x_load_store_unit_sva #(.DEPTH (DEPTH), .DEBUG(DEBUG)) load_store_unit_sva (
257260
// The SVA's monitor modport can't connect to a master modport, so it is connected to the interface instance directly:
258261
.m_c_obi_data_if(core_i.m_c_obi_data_if),
259262
.ex_wb_pipe_i (core_i.ex_wb_pipe),
@@ -319,6 +322,7 @@ module cv32e40x_wrapper
319322
bind cv32e40x_core:
320323
core_i cv32e40x_core_sva
321324
#(.A_EXT(A_EXT),
325+
.DEBUG (DEBUG),
322326
.PMA_NUM_REGIONS(PMA_NUM_REGIONS),
323327
.SMCLIC(SMCLIC))
324328
core_sva (// probed cs_registers signals
@@ -395,6 +399,7 @@ endgenerate
395399
.IS_INSTR_SIDE (1),
396400
.CORE_RESP_TYPE (cv32e40x_pkg::inst_resp_t),
397401
.CORE_REQ_TYPE (cv32e40x_pkg::obi_inst_req_t),
402+
.DEBUG (DEBUG),
398403
.DM_REGION_START (DM_REGION_START),
399404
.DM_REGION_END (DM_REGION_END))
400405
mpu_if_sva(.pma_addr (pma_i.trans_addr_i),
@@ -420,6 +425,7 @@ endgenerate
420425
.CORE_RESP_TYPE (cv32e40x_pkg::data_resp_t),
421426
.CORE_REQ_TYPE (cv32e40x_pkg::obi_data_req_t),
422427
.A_EXT (A_EXT),
428+
.DEBUG (DEBUG),
423429
.DM_REGION_START (DM_REGION_START),
424430
.DM_REGION_END (DM_REGION_END))
425431
mpu_lsu_sva(.pma_addr (pma_i.trans_addr_i),
@@ -463,7 +469,8 @@ endgenerate
463469
bind cv32e40x_rvfi:
464470
rvfi_i
465471
cv32e40x_rvfi_sva
466-
#(.SMCLIC(SMCLIC))
472+
#(.SMCLIC(SMCLIC),
473+
.DEBUG (DEBUG))
467474
rvfi_sva(.irq_ack(core_i.irq_ack),
468475
.dbg_ack(core_i.dbg_ack),
469476
.ebreak_in_wb_i(core_i.controller_i.controller_fsm_i.ebreak_in_wb),
@@ -488,7 +495,8 @@ endgenerate
488495
);
489496

490497
cv32e40x_rvfi
491-
#(.SMCLIC(SMCLIC))
498+
#(.SMCLIC(SMCLIC),
499+
.DEBUG (DEBUG))
492500
rvfi_i
493501
(.clk_i ( clk_i ),
494502
.rst_ni ( rst_ni ),
@@ -769,6 +777,7 @@ endgenerate
769777
.SMCLIC ( SMCLIC ),
770778
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ),
771779
.SMCLIC_INTTHRESHBITS ( SMCLIC_INTTHRESHBITS ),
780+
.DEBUG ( DEBUG ),
772781
.DM_REGION_START ( DM_REGION_START ),
773782
.DM_REGION_END ( DM_REGION_END ),
774783
.DBG_NUM_TRIGGERS ( DBG_NUM_TRIGGERS ),

‎rtl/cv32e40x_controller.sv

+4-2
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,8 @@ module cv32e40x_controller import cv32e40x_pkg::*;
3535
parameter bit A_EXT = 0,
3636
parameter int unsigned REGFILE_NUM_READ_PORTS = 2,
3737
parameter bit SMCLIC = 0,
38-
parameter int SMCLIC_ID_WIDTH = 5
38+
parameter int SMCLIC_ID_WIDTH = 5,
39+
parameter int DEBUG = 1
3940
)
4041
(
4142
input logic clk, // Gated clock
@@ -147,7 +148,8 @@ module cv32e40x_controller import cv32e40x_pkg::*;
147148
#(
148149
.X_EXT ( X_EXT ),
149150
.SMCLIC ( SMCLIC ),
150-
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH )
151+
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ),
152+
.DEBUG ( DEBUG )
151153
)
152154
controller_fsm_i
153155
(

‎rtl/cv32e40x_controller_fsm.sv

+1
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@
3232
module cv32e40x_controller_fsm import cv32e40x_pkg::*;
3333
#(
3434
parameter bit X_EXT = 0,
35+
parameter int DEBUG = 1,
3536
parameter bit SMCLIC = 0,
3637
parameter int SMCLIC_ID_WIDTH = 5
3738
)

‎rtl/cv32e40x_core.sv

+16-2
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@ module cv32e40x_core import cv32e40x_pkg::*;
3636
parameter bit A_EXT = 0,
3737
parameter b_ext_e B_EXT = B_NONE,
3838
parameter m_ext_e M_EXT = M,
39+
parameter int DEBUG = 1,
3940
parameter logic [31:0] DM_REGION_START = 32'hF0000000,
4041
parameter logic [31:0] DM_REGION_END = 32'hF0003FFF,
4142
parameter int DBG_NUM_TRIGGERS = 1,
@@ -183,6 +184,9 @@ module cv32e40x_core import cv32e40x_pkg::*;
183184
ctrl_byp_t ctrl_byp;
184185
ctrl_fsm_t ctrl_fsm;
185186

187+
// Gated debug_req_i signal depending on DEBUG parameter
188+
logic debug_req_gated;
189+
186190
// Register File Write Back
187191
logic rf_we_wb;
188192
rf_addr_t rf_waddr_wb;
@@ -393,6 +397,9 @@ module cv32e40x_core import cv32e40x_pkg::*;
393397
assign irq_shv = ctrl_fsm.irq_shv;
394398
assign dbg_ack = ctrl_fsm.dbg_ack;
395399

400+
// Gate off the internal debug_request signal if debug support is not configured.
401+
assign debug_req_gated = DEBUG ? debug_req_i : 1'b0;
402+
396403
//////////////////////////////////////////////////////////////////////////////////////////////
397404
// ____ _ _ __ __ _ //
398405
// / ___| | ___ ___| | __ | \/ | __ _ _ __ __ _ __ _ ___ _ __ ___ ___ _ __ | |_ //
@@ -452,6 +459,7 @@ module cv32e40x_core import cv32e40x_pkg::*;
452459
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ),
453460
.ZC_EXT ( ZC_EXT ),
454461
.M_EXT ( M_EXT ),
462+
.DEBUG ( DEBUG ),
455463
.DM_REGION_START ( DM_REGION_START ),
456464
.DM_REGION_END ( DM_REGION_END )
457465
)
@@ -647,6 +655,7 @@ module cv32e40x_core import cv32e40x_pkg::*;
647655
.PMA_NUM_REGIONS (PMA_NUM_REGIONS ),
648656
.PMA_CFG (PMA_CFG ),
649657
.DBG_NUM_TRIGGERS (DBG_NUM_TRIGGERS ),
658+
.DEBUG (DEBUG ),
650659
.DM_REGION_START (DM_REGION_START ),
651660
.DM_REGION_END (DM_REGION_END )
652661
)
@@ -715,6 +724,9 @@ module cv32e40x_core import cv32e40x_pkg::*;
715724
////////////////////////////////////////////////////////////////////////////////////////
716725

717726
cv32e40x_wb_stage
727+
#(
728+
.DEBUG ( DEBUG )
729+
)
718730
wb_stage_i
719731
(
720732
.clk ( clk ), // Not used in RTL; only used by assertions
@@ -784,6 +796,7 @@ module cv32e40x_core import cv32e40x_pkg::*;
784796
.SMCLIC ( SMCLIC ),
785797
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ),
786798
.SMCLIC_INTTHRESHBITS ( SMCLIC_INTTHRESHBITS ),
799+
.DEBUG ( DEBUG ),
787800
.DBG_NUM_TRIGGERS ( DBG_NUM_TRIGGERS ),
788801
.NUM_MHPMCOUNTERS ( NUM_MHPMCOUNTERS ),
789802
.MTVT_ADDR_WIDTH ( MTVT_ADDR_WIDTH )
@@ -878,7 +891,8 @@ module cv32e40x_core import cv32e40x_pkg::*;
878891
.A_EXT ( A_EXT ),
879892
.REGFILE_NUM_READ_PORTS ( REGFILE_NUM_READ_PORTS ),
880893
.SMCLIC ( SMCLIC ),
881-
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH )
894+
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ),
895+
.DEBUG ( DEBUG )
882896
)
883897
controller_i
884898
(
@@ -958,7 +972,7 @@ module cv32e40x_core import cv32e40x_pkg::*;
958972
.csr_wr_in_wb_flush_i ( csr_wr_in_wb_flush ),
959973

960974
// Debug signals
961-
.debug_req_i ( debug_req_i ),
975+
.debug_req_i ( debug_req_gated ),
962976
.dcsr_i ( dcsr ),
963977

964978
// Register File read, write back and forwards

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