Merge pull request #537 from Silabs-ArjanB/ArjanB_mcontrol6_m

etrigger.m and mcontrol6.m are now fully implemented (reset values changed as well)

Author: silabs-oysteink

docs/user_manual/source/control_status_registers.rst

@@ -1309,7 +1309,7 @@ Match Control Type 6 (``mcontrol6``)
 
 CSR Address: 0x7A1
 
-Reset Value: 0x6800_1044
+Reset Value: 0x6800_1000
 
 Accessible in Debug Mode or M-Mode, depending on **tdata1.dmode**.
 
@@ -1343,7 +1343,7 @@ Accessible in Debug Mode or M-Mode, depending on **tdata1.dmode**.
 ||      || (0x0, 0x2, ||            2: Address is greater than or equal to `tdata2`    |
 ||      ||  0x3)      ||            3: Address is less than `tdata2`                   |
 +-------+-------------+----------------------------------------------------------------+
-| 6     | WARL (0x1)  | **M**. Match in M-Mode.                                        |
+| 6     | WARL        | **M**. Match in M-Mode.                                        |
 +-------+-------------+----------------------------------------------------------------+
 | 5     | WARL (0x0)  | Hardwired to 0.                                                |
 +-------+-------------+----------------------------------------------------------------+
@@ -1365,14 +1365,14 @@ Exception Trigger (``etrigger``)
 
 CSR Address: 0x7A1
 
-Reset Value: 0x5800_0201
+Reset Value: 0x5800_0001
 
 Accessible in Debug Mode or M-Mode, depending on **tdata1.dmode**.
 
 +-------+--------------+----------------------------------------------------------------+
 | Bit#  | R/W          | Description                                                    |
 +=======+==============+================================================================+
-| 31:28 | WARL  (0x5)  | **TYPE**. 5 = Exception trigger.                               |
+| 31:28 | WARL (0x5)   | **TYPE**. 5 = Exception trigger.                               |
 +-------+--------------+----------------------------------------------------------------+
 | 27    | WARL (0x1)   | **DMODE**. Only debug mode can write tdata registers           |
 +-------+--------------+----------------------------------------------------------------+
@@ -1386,7 +1386,7 @@ Accessible in Debug Mode or M-Mode, depending on **tdata1.dmode**.
 +-------+--------------+----------------------------------------------------------------+
 | 10    | WARL         | **NMI**. Set to enable trigger on NMI.                         |
 +-------+--------------+----------------------------------------------------------------+
-| 9     | WARL (0x1)   | **M**. Match in M-Mode.                                        |
+| 9     | WARL         | **M**. Match in M-Mode.                                        |
 +-------+--------------+----------------------------------------------------------------+
 | 8     | WARL (0x0)   | Hardwired to 0.                                                |
 +-------+--------------+----------------------------------------------------------------+