diff --git a/rtl/cv32e40x_controller_bypass.sv b/rtl/cv32e40x_controller_bypass.sv index c8d57fcd..46a5fd96 100644 --- a/rtl/cv32e40x_controller_bypass.sv +++ b/rtl/cv32e40x_controller_bypass.sv @@ -97,7 +97,7 @@ module cv32e40x_controller_bypass import cv32e40x_pkg::*; assign lsu_en_wb = ex_wb_pipe_i.lsu_en && ex_wb_pipe_i.instr_valid; assign rf_waddr_ex = id_ex_pipe_i.rf_waddr; - assign rf_waddr_wb = ex_wb_pipe_i.rf_waddr; // TODO: If XIF OoO is allowed, we need to look at WB stage outputs instead + assign rf_waddr_wb = ex_wb_pipe_i.rf_waddr; // TODO:XIF If XIF OoO is allowed, we need to look at WB stage outputs instead // The following unqualified signals are such that they can have a false positive (but no false negative). // diff --git a/rtl/cv32e40x_controller_fsm.sv b/rtl/cv32e40x_controller_fsm.sv index db0c4893..47937e69 100644 --- a/rtl/cv32e40x_controller_fsm.sv +++ b/rtl/cv32e40x_controller_fsm.sv @@ -500,7 +500,7 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*; // synchronous debug entry have far fewer restrictions than asynchronous entries. In principle synchronous debug entry should have the same // 'allowed' signal as exceptions - that is it should always be possible. - // todo: When XIF is being finished, debug entry vs xif must be reevaluated. + // todo:XIF When XIF is being finished, debug entry vs xif must be reevaluated. assign sync_debug_allowed = !xif_in_wb && !(ctrl_fsm_cs == SLEEP); // Debug pending for any other synchronous reason than single step @@ -1466,7 +1466,7 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*; logic commit_kill_q; // Sticky bit for commit_kill logic kill_rejected; // Signal used to kill rejected xif instructions - // TODO: Add assertion to check the following: + // TODO:XIF Add assertion to check the following: // Every issue interface transaction (whether accepted or not) has an associated commit interface // transaction and both interfaces use a matching transaction ordering. diff --git a/rtl/cv32e40x_cs_registers.sv b/rtl/cv32e40x_cs_registers.sv index d8a71318..759bb9ee 100644 --- a/rtl/cv32e40x_cs_registers.sv +++ b/rtl/cv32e40x_cs_registers.sv @@ -34,7 +34,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; parameter m_ext_e M_EXT = M, parameter bit X_EXT = 0, parameter logic [31:0] X_MISA = 32'h00000000, - parameter logic [1:0] X_ECS_XS = 2'b00, // todo: implement related mstatus bitfields (but only if X_EXT = 1) + parameter logic [1:0] X_ECS_XS = 2'b00, // todo:XIF implement related mstatus bitfields (but only if X_EXT = 1) parameter bit ZC_EXT = 0, parameter bit CLIC = 0, parameter int unsigned CLIC_ID_WIDTH = 5, @@ -706,7 +706,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; tcontrol_we = 1'b0; - // TODO: add support for SD/XS/FS/VS + // TODO:XIF add support for SD/XS/FS/VS mstatus_n = csr_next_value(mstatus_t'{ tw: 1'b0, mprv: mstatus_mprv_resolve(mstatus_rdata.mprv, csr_wdata_int[MSTATUS_MPRV_BIT]), diff --git a/rtl/cv32e40x_ex_stage.sv b/rtl/cv32e40x_ex_stage.sv index ec80efb4..7c0b1560 100644 --- a/rtl/cv32e40x_ex_stage.sv +++ b/rtl/cv32e40x_ex_stage.sv @@ -479,7 +479,7 @@ module cv32e40x_ex_stage import cv32e40x_pkg::*; assign xif_valid = 1'b1; assign xif_ready = wb_ready_i; - // TODO: The EX stage needs to be ready to receive a result from a single cycle offloaded + // TODO:XIF The EX stage needs to be ready to receive a result from a single cycle offloaded // instruction. In such case the result can be written into ex_wb_pipe_i.rf_wdata (as if the XIF // is a functional unit living in EX) and then typically a cycle later the result would get // written from ex_wb_pipe_i.rf_wdata into the registerfile. diff --git a/rtl/cv32e40x_id_stage.sv b/rtl/cv32e40x_id_stage.sv index 1385dfb1..e838b36a 100644 --- a/rtl/cv32e40x_id_stage.sv +++ b/rtl/cv32e40x_id_stage.sv @@ -339,7 +339,7 @@ module cv32e40x_id_stage import cv32e40x_pkg::*; always_comb begin: jalr_fw_mux case (ctrl_byp_i.jalr_fw_mux_sel) - SELJ_FW_WB: jalr_fw = ex_wb_pipe_i.rf_wdata; // todo: This won't allow forwarding from the XIF. + SELJ_FW_WB: jalr_fw = ex_wb_pipe_i.rf_wdata; // todo:XIF This won't allow forwarding from the XIF. SELJ_REGFILE: jalr_fw = rf_rdata_i[0]; default: jalr_fw = rf_rdata_i[0]; endcase @@ -495,7 +495,7 @@ module cv32e40x_id_stage import cv32e40x_pkg::*; // Speculatively read all source registers for illegal instr, might be required by coprocessor // Non-offloaded instructions will use maximum two read ports (rf_re from decoder is two bits, rf_re_o may be two or three bits wide) - // Todo: Too conservative, causes load_use stalls on offloaded instruction when the operands may not be needed at all. + // Todo:XIF Too conservative, causes load_use stalls on offloaded instruction when the operands may not be needed at all. // issue_valid depends on halt_id (and data_rvalid) via the local instr_valid. // Can issue_valid be made fast by using the registered instr_valid and only factor in kill_id and not halt_id? // Maybe it is ok to have a late issue_valid, as accept signal will depend on late rs_valid anyway? @@ -725,7 +725,7 @@ module cv32e40x_id_stage import cv32e40x_pkg::*; if (X_EXT) begin : x_ext // remember whether an instruction was accepted or rejected (required if EX stage is not ready) - // TODO: check whether this state machine should be put back in its initial state when the instruction in ID gets killed + // TODO:XIF check whether this state machine should be put back in its initial state when the instruction in ID gets killed logic xif_accepted_q, xif_rejected_q; assign xif_en = xif_insn_accept || xif_insn_reject; @@ -771,17 +771,17 @@ module cv32e40x_id_stage import cv32e40x_pkg::*; xif_issue_if.issue_req.rs [1] = operand_b_fw; xif_issue_if.issue_req.rs_valid[1] = !rf_illegal_raddr[1]; end - // TODO: implement forwarding for other operands than rs1 and rs2 + // TODO:XIF implement forwarding for other operands than rs1 and rs2 for (integer i = 2; i < xif_issue_if.X_NUM_RS && i < REGFILE_NUM_READ_PORTS; i++) begin xif_issue_if.issue_req.rs [i] = rf_rdata_i[i]; xif_issue_if.issue_req.rs_valid[i] = !rf_illegal_raddr[i]; end end - assign xif_issue_if.issue_req.ecs = 6'b111111; // todo: hookup to related mstatus bits (for now just reporting all state as dirty) + assign xif_issue_if.issue_req.ecs = 6'b111111; // todo:XIF hookup to related mstatus bits (for now just reporting all state as dirty) // and make sure that instruction after ecs update sees correct bits - assign xif_issue_if.issue_req.ecs_valid = 1'b1; // todo: needs to take into account if mstatus extension context writes are in flight - // todo: use xif_issue_if.issue_resp.ecswrite + assign xif_issue_if.issue_req.ecs_valid = 1'b1; // todo:XIF needs to take into account if mstatus extension context writes are in flight + // todo:XIF use xif_issue_if.issue_resp.ecswrite // need to wait if the coprocessor is not ready and has not already accepted or rejected the instruction assign xif_waiting = xif_issue_if.issue_valid && !xif_issue_if.issue_ready && !xif_accepted_q && !xif_rejected_q; @@ -790,7 +790,7 @@ module cv32e40x_id_stage import cv32e40x_pkg::*; assign xif_insn_accept = (xif_issue_if.issue_valid && xif_issue_if.issue_ready && xif_issue_if.issue_resp.accept) || xif_accepted_q; assign xif_insn_reject = (xif_issue_if.issue_valid && xif_issue_if.issue_ready && !xif_issue_if.issue_resp.accept) || xif_rejected_q; - // TODO: These may be missed if issue_valid retracts before ID goes to EX. Need to check for sticky accept as well + // TODO:XIF These may be missed if issue_valid retracts before ID goes to EX. Need to check for sticky accept as well assign xif_we = xif_issue_if.issue_valid && xif_issue_if.issue_resp.writeback; assign xif_exception = xif_issue_if.issue_valid && xif_issue_if.issue_resp.exc; assign xif_dualwrite = xif_issue_if.issue_valid && xif_issue_if.issue_resp.dualwrite; diff --git a/rtl/cv32e40x_if_stage.sv b/rtl/cv32e40x_if_stage.sv index 2c4235b3..55961e2d 100644 --- a/rtl/cv32e40x_if_stage.sv +++ b/rtl/cv32e40x_if_stage.sv @@ -555,11 +555,11 @@ module cv32e40x_if_stage import cv32e40x_pkg::*; generate if (X_EXT) begin : x_ext - // TODO: implement offloading of compressed instruction + // TODO:XIF implement offloading of compressed instruction assign xif_compressed_if.compressed_valid = '0; assign xif_compressed_if.compressed_req = '0; - // TODO: assert that the oustanding IDs are unique + // TODO:XIF assert that the oustanding IDs are unique assign xif_id = xif_offloading_id_i ? if_id_pipe_o.xif_id + 1 : if_id_pipe_o.xif_id; end else begin : no_x_ext diff --git a/rtl/cv32e40x_load_store_unit.sv b/rtl/cv32e40x_load_store_unit.sv index b11b6648..5897dab0 100644 --- a/rtl/cv32e40x_load_store_unit.sv +++ b/rtl/cv32e40x_load_store_unit.sv @@ -514,7 +514,7 @@ module cv32e40x_load_store_unit import cv32e40x_pkg::*; wpt_trans.wdata = xif_mem_if.mem_req.wdata; wpt_trans.atop = '0; wpt_trans.prot = {xif_mem_if.mem_req.mode, 1'b1}; // XIF transfers are data transfers - wpt_trans.dbg = '0; // TODO setup debug triggers + wpt_trans.dbg = '0; // TODO:XIF setup debug triggers wpt_trans.memtype = 2'b00; // Memory type is assigned in MPU end else begin // For last phase of misaligned/split transfer the address needs to be word aligned (as LSB of be will be set) @@ -552,7 +552,7 @@ module cv32e40x_load_store_unit import cv32e40x_pkg::*; // LSU second stage is valid when resp_valid (typically data_rvalid_i) is received. Both parts of a misaligned transfer will signal valid_1_o. assign valid_1_o = resp_valid && valid_1_i && !xif_res_q; - assign xif_mem_result_if.mem_result_valid = last_q && resp_valid && xif_res_q; // todo: last_q or not? + assign xif_mem_result_if.mem_result_valid = last_q && resp_valid && xif_res_q; // todo:XIF last_q or not? // LSU EX stage readyness requires two criteria to be met: // @@ -840,7 +840,7 @@ module cv32e40x_load_store_unit import cv32e40x_pkg::*; .core_one_txn_pend_n ( cnt_is_one_next ), .core_align_err_wait_i( consumer_resp_wait ), - .core_align_err_o ( ), // todo: Unconnected on purpose, is this needed for xif? + .core_align_err_o ( ), // todo:XIF Unconnected on purpose, is this needed for xif? .core_trans_valid_i ( alcheck_trans_valid ), .core_trans_ready_o ( alcheck_trans_ready ), @@ -944,7 +944,7 @@ module cv32e40x_load_store_unit import cv32e40x_pkg::*; assign xif_mem_result_if.mem_result.id = xif_id_q; assign xif_mem_result_if.mem_result.rdata = rdata_ext; assign xif_mem_result_if.mem_result.err = filter_err[0]; // forward bus errors to coprocessor - assign xif_mem_result_if.mem_result.dbg = '0; // TODO forward debug triggers + assign xif_mem_result_if.mem_result.dbg = '0; // TODO:XIF forward debug triggers end else begin : no_x_ext assign xif_mem_if.mem_resp.exc = '0; assign xif_mem_if.mem_resp.exccode = '0; diff --git a/rtl/cv32e40x_wb_stage.sv b/rtl/cv32e40x_wb_stage.sv index a7913590..ebbacf20 100644 --- a/rtl/cv32e40x_wb_stage.sv +++ b/rtl/cv32e40x_wb_stage.sv @@ -129,11 +129,11 @@ module cv32e40x_wb_stage import cv32e40x_pkg::*; // In case of MPU/PMA error, the register file should not be written. // rf_we_wb_o is deasserted if lsu_mpu_status is not equal to MPU_OK - // TODO: Could use result interface.we into account if out of order completion is allowed. + // TODO:XIF Could use result interface.we into account if out of order completion is allowed. assign rf_we_wb_o = ex_wb_pipe_i.rf_we && !lsu_exception && !xif_waiting && !xif_exception && !lsu_wpt_match && instr_valid; - // TODO: Could use result interface.rd into account if out of order completion is allowed. + // TODO:XIF Could use result interface.rd into account if out of order completion is allowed. assign rf_waddr_wb_o = ex_wb_pipe_i.rf_waddr; - // TODO: Could use result interface.rd into account if out of order completion is allowed. + // TODO:XIF Could use result interface.rd into account if out of order completion is allowed. // Not using any flopped/sticky version of lsu_rdata_i. The sticky bits are only needed for MPU errors and watchpoint triggers. // Any true load that succeeds will write the RF and will never be halted or killed by the controller. (wb_valid during the same cycle as lsu_valid_i). assign rf_wdata_wb_o = ex_wb_pipe_i.lsu_en ? lsu_rdata_i : @@ -220,19 +220,19 @@ module cv32e40x_wb_stage import cv32e40x_pkg::*; // eXtension interface //--------------------------------------------------------------------------- - // TODO: How to handle conflicting values of ex_wb_pipe_i.rf_waddr and xif_result_if.result.rd? - // TODO: How to handle conflicting values of ex_wb_pipe_i.rf_we (based on xif_issue_if.issue_resp.writeback in ID) and xif_result_if.result.we? - // TODO: Check whether result IDs match the instruction IDs propagated along the pipeline - // TODO: Implement writeback to extension context status into mstatus (ecswe, ecsdata) + // TODO:XIF How to handle conflicting values of ex_wb_pipe_i.rf_waddr and xif_result_if.result.rd? + // TODO:XIF How to handle conflicting values of ex_wb_pipe_i.rf_we (based on xif_issue_if.issue_resp.writeback in ID) and xif_result_if.result.we? + // TODO:XIF Check whether result IDs match the instruction IDs propagated along the pipeline + // TODO:XIF Implement writeback to extension context status into mstatus (ecswe, ecsdata) // Need to wait for the result assign xif_waiting = ex_wb_pipe_i.instr_valid && ex_wb_pipe_i.xif_en && !xif_result_if.result_valid; // Coprocessor signals a synchronous exception - // TODO: Maybe do something when an exception occurs (other than just inhibiting writeback) + // TODO:XIF Maybe do something when an exception occurs (other than just inhibiting writeback) assign xif_exception = ex_wb_pipe_i.instr_valid && ex_wb_pipe_i.xif_en && xif_result_if.result_valid && xif_result_if.result.exc; - // todo: Handle xif_result_if.result.err as NMI (do not factor into xif_exception as that signal is for synchronous exceptions) + // todo:XIF Handle xif_result_if.result.err as NMI (do not factor into xif_exception as that signal is for synchronous exceptions) assign xif_result_if.result_ready = ex_wb_pipe_i.instr_valid && ex_wb_pipe_i.xif_en;