Stylistic fixes to get the pipeline back running.

Author: yvantor

rtl/redmule_ctrl.sv

@@ -3,7 +3,7 @@
 // SPDX-License-Identifier: SHL-0.51
 //
 // Yvan Tortorella <[email protected]>
-// Andrea Belano <[email protected]> 
+// Andrea Belano <[email protected]>
 //
 
 import redmule_pkg::*;

rtl/redmule_memory_scheduler.sv

@@ -1,3 +1,10 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Andrea Belano <[email protected]>
+//
+
 module redmule_memory_scheduler
   import redmule_pkg::*;
   import hwpe_ctrl_package::*;
@@ -36,7 +43,7 @@ module redmule_memory_scheduler
   logic [$clog2(W):0] x_rows_lftover_d, x_rows_lftover_q;
 
   logic [$clog2(W):0] num_x_reads;
- 
+
   always_ff @(posedge clk_i or negedge rst_ni) begin : x_cols_iters_register
     if (~rst_ni) begin
         x_cols_iters_q <= '0;
@@ -64,7 +71,7 @@ module redmule_memory_scheduler
   end
 
   assign w_iters_d = w_iters_q == reg_file_i.hwpe_params[W_ITERS][15:0]-1 ? '0 : w_iters_q + 1;
-  
+
   always_ff @(posedge clk_i or negedge rst_ni) begin : x_rows_iters_register
     if (~rst_ni) begin
       x_rows_iters_q <= '0;
@@ -139,7 +146,7 @@ module redmule_memory_scheduler
 
     // Here we initialize the streamer source signals
     // for the W stream source
-    // In quantization mode this is used to load the scales instead 
+    // In quantization mode this is used to load the scales instead
     if (reg_file_i.hwpe_params[DEQUANT_MODE][0] == 1'b0) begin
       cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.base_addr = reg_file_i.hwpe_params[W_ADDR];
       cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.tot_len = reg_file_i.hwpe_params[W_TOT_LEN];
@@ -222,7 +229,7 @@ module redmule_memory_scheduler
   always_comb begin : req_start_assignment
     cntrl_streamer_o.x_stream_source_ctrl.req_start     = (cntrl_scheduler_i.first_load || tot_x_read_q != '0 && tot_x_read_q != reg_file_i.hwpe_params[TOT_X_READ]) && flgs_streamer_i.x_stream_source_flags.ready_start;
     cntrl_streamer_o.w_stream_source_ctrl.req_start     = cntrl_scheduler_i.first_load && flgs_streamer_i.z_stream_sink_flags.ready_start;
-    cntrl_streamer_o.y_stream_source_ctrl.req_start     = cntrl_scheduler_i.first_load && reg_file_i.hwpe_params[OP_SELECTION][0] && flgs_streamer_i.y_stream_source_flags.ready_start; 
+    cntrl_streamer_o.y_stream_source_ctrl.req_start     = cntrl_scheduler_i.first_load && reg_file_i.hwpe_params[OP_SELECTION][0] && flgs_streamer_i.y_stream_source_flags.ready_start;
     cntrl_streamer_o.z_stream_sink_ctrl.req_start       = cntrl_scheduler_i.first_load && flgs_streamer_i.z_stream_sink_flags.ready_start;
     cntrl_streamer_o.gid_stream_source_ctrl.req_start   = '0; //FIXME
     cntrl_streamer_o.wq_stream_source_ctrl.req_start    = '0; //FIXME
@@ -234,4 +241,4 @@ module redmule_memory_scheduler
   assign cntrl_streamer_o.output_cast_src_fmt = fpnew_pkg::fp_format_e'(reg_file_i.hwpe_params[OP_SELECTION][12:10]);
   assign cntrl_streamer_o.output_cast_dst_fmt = fpnew_pkg::fp_format_e'(reg_file_i.hwpe_params[OP_SELECTION][15:13]);
 
-endmodule
+endmodule : redmule_memory_scheduler

rtl/redmule_pkg.sv

@@ -99,7 +99,7 @@ package redmule_pkg;
   // [2:1]   -> Quantized format
   // [0:0]   -> Dequantization enable
   parameter int unsigned DEQUANT_MODE = 18; // 0x48
-  parameter int unsigned GIDX_ADDR    = 19; // 0x4C  
+  parameter int unsigned GIDX_ADDR    = 19; // 0x4C
   parameter int unsigned SCALES_ADDR  = 20; // 0x50
   parameter int unsigned ZEROS_ADDR   = 21; // 0x54
 

rtl/redmule_scheduler.sv

@@ -2,6 +2,7 @@
 // Solderpad Hardware License, Version 0.51, see LICENSE for details.
 // SPDX-License-Identifier: SHL-0.51
 //
+// Yvan Tortorella <[email protected]>
 // Andrea Belano <[email protected]>
 //
 
@@ -168,7 +169,7 @@ module redmule_scheduler
 
   assign x_shift_cnt_en = (current_state == LOAD_W) && ~stall_engine;
   assign x_shift_cnt_d  = x_shift_cnt_q == H-1 ? '0 : x_shift_cnt_q + 1;
-  
+
   assign cntrl_x_buffer_o.h_shift = x_shift_cnt_en;
   assign cntrl_x_buffer_o.d_shift = x_shift_cnt_q == H-1 && x_shift_cnt_en;
 
@@ -194,7 +195,7 @@ module redmule_scheduler
 
   assign x_reload_en  = start || x_cols_iter_en/*x_w_iters_en*/;
   assign x_reload_rst = flgs_x_buffer_i.full;
-  
+
   assign cntrl_x_buffer_o.pad_setup   = current_state == PRELOAD && next_state == LOAD_W;
   assign cntrl_x_buffer_o.load        = (flgs_x_buffer_i.empty || x_reload_q) && x_valid_i;
   assign cntrl_x_buffer_o.rst_w_index = (current_state == LOAD_W && x_shift_cnt_q == H-1) && flgs_x_buffer_i.full && ~stall_engine; // FIXME CHECK, WAS current_state == LOAD_W && flgs_x_buffer_i.full
@@ -271,7 +272,7 @@ module redmule_scheduler
 
   assign cntrl_w_buffer_o.height = w_rows_iter_q >= reg_file_i.hwpe_params[W_ITERS][31:16]-(PIPE_REGS+1)/*w_cols_iter_q == reg_file_i.hwpe_params[W_ITERS][15:0]-1*/ && reg_file_i.hwpe_params[LEFTOVERS][15:8] != '0 ? reg_file_i.hwpe_params[LEFTOVERS][15:8] : H;
   assign cntrl_w_buffer_o.width  = w_cols_iter_q == reg_file_i.hwpe_params[W_ITERS][15:0]-1/*w_rows_iter_q >= reg_file_i.hwpe_params[W_ITERS][31:16]-(PIPE_REGS+1)*/ && reg_file_i.hwpe_params[LEFTOVERS][7:0] != '0 ? reg_file_i.hwpe_params[LEFTOVERS][7:0] : D;
-  
+
   assign cntrl_w_buffer_o.load  = current_state == LOAD_W && ~stall_engine;
   assign cntrl_w_buffer_o.shift = (current_state == LOAD_W || current_state == WAIT) && ~stall_engine;
 
@@ -584,7 +585,7 @@ module redmule_scheduler
   assign flgs_scheduler_o.w_loaded = current_state == LOAD_W && ~stall_engine;
 
   /*********************************
-   *            FSM                * 
+   *            FSM                *
    *********************************/
 
   always_ff @(posedge clk_i or negedge rst_ni) begin : state_register
@@ -637,4 +638,4 @@ module redmule_scheduler
     endcase
   end
 
-endmodule
+endmodule : redmule_scheduler

rtl/redmule_top.sv

@@ -137,24 +137,24 @@ flags_fifo_t   w_fifo_flgs;
 // X streaming interface + X FIFO interface
 hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) x_buffer_d         ( .clk( clk_i ) );
 hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) x_buffer_fifo      ( .clk( clk_i ) );
- 
-// W streaming interface + W FIFO interface 
+
+// W streaming interface + W FIFO interface
 hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) w_buffer_d         ( .clk( clk_i ) );
 hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) w_buffer_fifo      ( .clk( clk_i ) );
- 
-// Y streaming interface + Y FIFO interface 
+
+// Y streaming interface + Y FIFO interface
 hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) y_buffer_d         ( .clk( clk_i ) );
 hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) y_buffer_fifo      ( .clk( clk_i ) );
- 
-// Z streaming interface + Z FIFO interface 
+
+// Z streaming interface + Z FIFO interface
 hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) z_buffer_q         ( .clk( clk_i ) );
 hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) z_buffer_fifo      ( .clk( clk_i ) );
 
 // GIDX streaming interface + GIDX FIFO interface
 hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) gidx_stream_d      ( .clk( clk_i ) );  //FIXME DATA WIDTH (?)
 hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) gidx_buffer_fifo   ( .clk( clk_i ) );
 
-hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) wq_stream_d    ( .clk( clk_i ) );  
+hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) wq_stream_d    ( .clk( clk_i ) );
 hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) wq_buffer_fifo ( .clk( clk_i ) );
 
 hwpe_stream_intf_stream #( .DATA_WIDTH ( DATAW_ALIGN ) ) zeros_stream_d     ( .clk( clk_i ) );  //FIXME DATA WIDTH
@@ -317,7 +317,7 @@ redmule_w_buffer #(
   .flags_o     ( w_buffer_flgs      ),
   .w_buffer_o  ( w_buffer_q         ),
   .w_buffer_i  ( w_buffer_fifo.data ),
-  .next_gidx_i ( wrow_q.data &'b111 )      //JUST FOR TESTING 
+  .next_gidx_i ( wrow_q.data &'b111 )      //JUST FOR TESTING
 );
 
 logic [Width-1:0][BITW-1:0] z_buffer_d, y_bias_q;
@@ -446,7 +446,7 @@ redmule_engine     #(
 redmule_memory_scheduler #(
   .DW (DATAW_ALIGN),
   .W  (Width),
-  .H  (Height) 
+  .H  (Height)
 ) i_memory_scheduler (
   .clk_i             ( clk_i               ),
   .rst_ni            ( rst_ni              ),
@@ -495,52 +495,6 @@ redmule_ctrl        #(
 /*---------------------------------------------------------------*/
 /* |                        Local FSM                          | */
 /*---------------------------------------------------------------*/
-
-//redmule_scheduler    #(
-//  .Height             ( Height              ),
-//  .Width              ( Width               ),
-//  .NumPipeRegs        ( NumPipeRegs         )
-//) i_scheduler         (
-//  .clk_i              ( clk_i               ),
-//  .rst_ni             ( rst_ni              ),
-//  .test_mode_i        ( test_mode_i         ),
-//  .clear_i            ( clear               ),
-//  .x_valid_i          ( x_buffer_fifo.valid ),
-//  .x_strb_i           ( x_buffer_fifo.strb  ),
-//  .w_valid_i          ( w_buffer_fifo.valid ),
-//  .w_strb_i           ( w_buffer_fifo.strb  ),
-//  .y_fifo_valid_i     ( y_buffer_fifo.valid ),
-//  .y_fifo_strb_i      ( y_buffer_fifo.strb  ),
-//  .z_ready_i          ( z_buffer_q.ready    ),
-//  .accumulate_i       ( accumulate          ),
-//  .engine_flush_i     ( engine_flush        ),
-//  .z_strb_o           (                     ),
-//  .soft_clear_o       ( soft_clear          ),
-//  .w_load_o           ( w_load              ),
-//  .w_cols_lftovr_o    ( w_cols_lftovr       ),
-//  .w_rows_lftovr_o    ( w_rows_lftovr       ),
-//  .y_cols_lftovr_o    ( y_cols_lftovr       ),
-//  .y_rows_lftovr_o    ( y_rows_lftovr       ),
-//  .gate_en_o          ( gate_en             ),
-//  .z_buffer_clk_en_o  ( fsm_z_clk_en        ),
-//  .reg_enable_o       ( reg_enable          ),
-//  .z_store_o          ( z_buffer_store      ),
-//  .y_buffer_load_o    ( y_buffer_load       ),
-//  .reg_file_i         ( reg_file            ),
-//  .flgs_streamer_i    ( flgs_streamer       ),
-//  .flgs_x_buffer_i    ( x_buffer_flgs       ),
-//  .flgs_w_buffer_i    ( w_buffer_flgs       ),
-//  .flgs_z_buffer_i    ( z_buffer_flgs       ),
-//  .flgs_engine_i      ( flgs_engine         ),
-//  .fifo_flgs_i        ( w_fifo_flgs         ),
-//  .cntrl_scheduler_i  ( cntrl_scheduler     ),
-//  .cntrl_engine_o     ( cntrl_engine        ),
-//  .cntrl_x_buffer_o   ( x_buffer_ctrl       ),
-//  .flgs_scheduler_o   ( flgs_scheduler      )
-//);
-
-
-// Will replace the scheduler
 redmule_scheduler #(
   .Height      ( Height         ),
   .Width       ( Width          ),

rtl/w_buffer/redmule_w_buffer.sv

@@ -17,7 +17,7 @@ module redmule_w_buffer
   parameter int unsigned  GID_WIDTH = GROUP_ID_WIDTH    ,
   localparam int unsigned BITW      = fp_width(FpFormat), // Number of bits for the given format
   localparam int unsigned H         = Height            ,
-  localparam int unsigned D         = DW/BITW           
+  localparam int unsigned D         = DW/BITW
 )(
   input  logic                             clk_i     ,
   input  logic                             rst_ni    ,
@@ -61,7 +61,7 @@ logic [$clog2(H)-1:0] buf_write_addr;
 
 logic [H-1:0][$clog2(N_REGS+1)+$clog2(C)+$clog2(H)-1:0] buf_read_addr;
 
-for (genvar d = 0; d < D; d++) begin : zero_padding
+for (genvar d = 0; d < D; d++) begin : gen_zero_padding
   assign w_data[d] = (d < ctrl_i.width && w_row < ctrl_i.height) ? w_buffer_i[(d+1)*BITW-1:d*BITW] : '0;
 end
 
@@ -164,7 +164,7 @@ for (genvar h = 0; h < H; h++) begin : gen_w_id_registers
   assign cache_w_id_valid_d[h] = (evict_pointer == h && ctrl_i.load && ctrl_i.dequant && ~gidx_present) ? '1 : cache_w_id_valid_q[h];
 end
 
-// Each row of the buffer has a counter that 
+// Each row of the buffer has a counter that
 // It resets to D/(PIPE_REGS+1)-1 each time the vector is requested
 for (genvar h = 0; h < H; h++) begin : gen_usage_counters
   always_ff @(posedge clk_i or negedge rst_ni) begin

rtl/w_buffer/redmule_w_buffer_scm.sv

@@ -9,7 +9,7 @@ module redmule_w_buffer_scm #(
   parameter int unsigned WORD_SIZE = 32,
   parameter int unsigned ROWS      = 1 ,
   parameter int unsigned COLS      = 1 ,
-  parameter int unsigned ELMS      = 1 
+  parameter int unsigned ELMS      = 1
 ) (
   input  logic                                                        clk_i            ,
   input  logic                                                        rst_ni           ,
@@ -51,7 +51,7 @@ module redmule_w_buffer_scm #(
     assign cols_read_addr[r] = cols_read_offs_q >= r ? cols_read_offs_q - r : ROWS - (r - cols_read_offs_q);
   end
 
-  for (genvar r = 0; r < ROWS; r++) begin : output_assignment
+  for (genvar r = 0; r < ROWS; r++) begin : gen_output_assignment
     assign rdata_o[r] = buffer_q[rows_read_addr_q[r]][cols_read_addr[r]][elms_read_addr_q];
   end
 
@@ -84,4 +84,4 @@ module redmule_w_buffer_scm #(
     end
   end
 
-endmodule
+endmodule : redmule_w_buffer_scm

rtl/x_buffer/redmule_x_buffer.sv

@@ -29,7 +29,7 @@ localparam int unsigned          TOT_DEPTH = H*D
   output logic                      [W-1:0][H-1:0][BITW-1:0] x_buffer_o ,
   input  logic                                      [DW-1:0] x_buffer_i ,
   input  logic                             [$clog2(D*H)-1:0] next_wrow_i,   //Tentative name
-  output logic                                               next_wrow_ready_o 
+  output logic                                               next_wrow_ready_o
 );
 
 typedef enum logic [2:0] {
@@ -108,7 +108,7 @@ redmule_x_pad_scm #(
 
 // Normally, we only write a row in the buffer when another one is read
 // In the FAST_FILL state we write a new row in the buffer every cycle until it is full
-assign buf_write_en = ( current_state == FAST_FILL || 
+assign buf_write_en = ( current_state == FAST_FILL ||
                         current_state == FILL && ctrl_i.h_shift)
                       && ~refilling;
 
@@ -186,7 +186,7 @@ always_comb begin : fsm
           end
         end
       end
-    end 
+    end
   endcase
 end
 

rtl/x_buffer/redmule_x_buffer_scm.sv

@@ -9,18 +9,18 @@ module redmule_x_buffer_scm #(
   parameter int unsigned WORD_SIZE = 32,
   parameter int unsigned WIDTH     = 1 ,
   parameter int unsigned HEIGHT    = 2 ,
-  parameter int unsigned N_OUTPUTS = 1 
+  parameter int unsigned N_OUTPUTS = 1
 ) (
   input  logic                                           clk_i        ,
   input  logic                                           rst_ni       ,
   input  logic                                           write_en_i   ,
   input  logic [$clog2(N_OUTPUTS)+$clog2(HEIGHT)-1:0]    write_addr_i ,
   input  logic [WIDTH-1:0][WORD_SIZE-1:0]                wdata_i      ,
   input  logic                                           read_en_i    ,
-  input  logic [$clog2(N_OUTPUTS)+$clog2(HEIGHT)-1:0]    read_addr_i  ,  
-  output logic [N_OUTPUTS-1:0][WIDTH-1:0][WORD_SIZE-1:0] rdata_o      
+  input  logic [$clog2(N_OUTPUTS)+$clog2(HEIGHT)-1:0]    read_addr_i  ,
+  output logic [N_OUTPUTS-1:0][WIDTH-1:0][WORD_SIZE-1:0] rdata_o
 );
-  logic [HEIGHT-1:0][N_OUTPUTS-1:0][WIDTH-1:0][WORD_SIZE-1:0] buffer_q; 
+  logic [HEIGHT-1:0][N_OUTPUTS-1:0][WIDTH-1:0][WORD_SIZE-1:0] buffer_q;
   logic [WIDTH-1:0][WORD_SIZE-1:0]                            wdata_q;
   logic [N_OUTPUTS-1:0][$clog2(HEIGHT)-1:0]                   read_addr_q;
 
@@ -41,7 +41,7 @@ module redmule_x_buffer_scm #(
     end
   end
 
-  for (genvar o = 0; o < N_OUTPUTS; o++) begin : output_assignment
+  for (genvar o = 0; o < N_OUTPUTS; o++) begin : gen_output_assignment
     assign rdata_o[o] = buffer_q[read_addr_q[o]][o];
   end
 
@@ -79,4 +79,4 @@ module redmule_x_buffer_scm #(
     end
   end
 
-endmodule
+endmodule : redmule_x_buffer_scm

rtl/x_buffer/redmule_x_pad_scm.sv

@@ -8,18 +8,18 @@
 module redmule_x_pad_scm #(
   parameter int unsigned WORD_SIZE = 32,
   parameter int unsigned ROWS      = 1 ,
-  parameter int unsigned COLS      = 1 
+  parameter int unsigned COLS      = 1
 ) (
   input  logic                           clk_i        ,
   input  logic                           rst_ni       ,
   input  logic                           write_en_i   ,
   input  logic [$clog2(ROWS)-1:0]        write_addr_i ,
   input  logic [COLS-1:0][WORD_SIZE-1:0] wdata_i      ,
   input  logic                           read_en_i    ,
-  input  logic [$clog2(COLS)-1:0]        read_addr_i  ,  
-  output logic [ROWS-1:0][WORD_SIZE-1:0] rdata_o      
+  input  logic [$clog2(COLS)-1:0]        read_addr_i  ,
+  output logic [ROWS-1:0][WORD_SIZE-1:0] rdata_o
 );
-  logic [ROWS-1:0][COLS-1:0][WORD_SIZE-1:0] buffer_q; 
+  logic [ROWS-1:0][COLS-1:0][WORD_SIZE-1:0] buffer_q;
   logic [COLS-1:0][WORD_SIZE-1:0]           wdata_q;
   logic [$clog2(COLS)-1:0]                  read_addr_q;
 
@@ -35,7 +35,7 @@ module redmule_x_pad_scm #(
     end
   end
 
-  for (genvar r = 0; r < ROWS; r++) begin : output_assignment
+  for (genvar r = 0; r < ROWS; r++) begin : gen_output_assignment
     assign rdata_o[r] = buffer_q[r][read_addr_q];
   end
 
@@ -68,4 +68,4 @@ module redmule_x_pad_scm #(
     end
   end
 
-endmodule
+endmodule : redmule_x_pad_scm