Updated to categorize options.

Author: kasanovic

rvb23-profile.adoc

@@ -91,7 +91,7 @@ instruction causes a requested trap to the execution environment.
 
 ==== RVB23U64 Mandatory Extensions
 
-The following mandatory extensions are also present in RVA22U64.
+The following mandatory extensions were also present in RVA22U64.
 
 - *M* Integer multiplication and division.
 - *A* Atomic instructions.
@@ -136,41 +136,71 @@ The following mandatory extensions are also present in RVA23U64:
 
 RVB23U64 has 18 profile options listed below.
 
-The following extensions are are mandatory in RVA23U64 but are
-optional in RVB23U64:
+===== Localized Options
+
+The following extensions are localized options in both RVA23U64 and RVB23U64:
+
+- *Zvbc* Vector carryless multiply.
+- *Zvkng* Vector Crypto NIST Algorithms including GHASH.
+- *Zvksg* Vector Crypto ShangMi Algorithms including GHASH.
+
+The following extensions options are localized options in RVB23U64 but
+are not present in RVA23U64:
+
+- *Zvkg* Vector GHASH instructions
+- *Zvknc* Vector Crypto NIST Algorithms with carryless multiply
+- *Zvksc* Vector Crypto ShangMi Algorithms with carryless multiply
+
+NOTE: RVA profiles mandate the higher-performing but more expensive
+GHASH options when adding vector crypto.  To reduce implementation
+cost, RVB profiles also allow these carryless multiply options (Zvknc
+and Zvksc) to implement GCM efficiently, with GHASH available as a
+separate option.
+
+===== Development Options
+
+The following are new development options intended to become mandatory in RVB24U64:
+
+- *Zacas* Compare-and-swap
+
+===== Expansion Options
+
+The following extensions are mandatory in RVA23U64 but are expansion
+options in RVB23U64:
+
+- *Zfhmin* Half-Precision Floating-point transfer and convert.
 
 - *V* Vector Extension.
 
 NOTE: Unclear if other Zve* extensions should also be supported in RVB.
 
-- *Zfhmin* Half-Precision Floating-point transfer and convert.
 - *Zvfhmin* Vector FP16 conversion instructions.
-
 - *Zvbb* Vector bitmanip extension.
+- *Zvkt* Vector data-independent execution time.
 
-The following extensions are optional in both RVB23U64 and RVA23U64:
+The following extensions are expansion options in both RVA23U64 and RVB23U64:
 
 - *Zfh* Scalar Half-Precision Floating-Point (FP16).
 - *Zbc* Scalar carryless multiply.
 - *Zvfh* Vector half-precision floating-point (FP16).
 - *Zfbfmin* Scalar BF16 FP conversions.
 - *Zvfbfmin* Vector BF16 FP conversions.
 - *Zvfbfwma* Vector BF16 widening mul-add.
+- *Zama16b* Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic.
 
-- *Zvbc* Vector carryless multiply.
-- *Zvkng* Vector Crypto NIST Algorithms including GHASH.
-- *Zvksg* Vector Crypto ShangMi Algorithms including GHASH.
-
-The following options are optional in RVB23U64 but are not present in
-RVA23U64:
+The following are RVA23U64 development options as they are intended to
+become mandatory in RVA24U64 profile, but are considered expansion
+options for RVB23U64 as they are not intended to be made mandatory in
+RVB profiles:
 
-- *Zvkg* Vector GHASH instructions
-- *Zvknc* Vector Crypto NIST Algorithms with carryless multiply
-- *Zvksc* Vector Crypto ShangMi Algorithms with carryless multiply
+- *Zvbc* Vector carryless multiply.
 
+===== Transitory Options
 
-NOTE: If either of Zvkn or Zvks is implemented, RVB mandates at least some support to implement GCM efficiently through either Zvbc or Zvkg.
+There are no transitory options in RVA23U64.
 
+NOTE: Scalar crypto is no longer an option in RVA23U64, though the Zbc
+extension has now been exposed as an expansion option.
 
 ==== RVB23U64 Recommendations
 
@@ -221,8 +251,6 @@ NOTE: Ss1p13 supersedes Ss1p12 but is not yet ratified.
 NOTE: Svnapot is very low cost to provide, so is made mandatory even
 in RVB.
 
-The following privileged extensions were also mandatory in RVA22S64:
-
 - *Svbare* The `satp` mode Bare must be supported.
 
 - *Sv39* Page-Based 39-bit Virtual-Memory System.
@@ -251,12 +279,12 @@ The following privileged extensions were also mandatory in RVA22S64:
 
 - *Svinval* Fine-Grained Address-Translation Cache Invalidation
 
-- *Ssu64xl* `sstatus.UXL` must be capable of holding the value 2
-(i.e., UXLEN=64 must be supported).
-
 - *Sstc* supervisor-mode timer interrupts.
 
-NOTE: Sstc was optional in RVA22.
+- *Sscofpmf* Count Overflow and Mode-Based Filtering.
+
+- *Ssu64xl* `sstatus.UXL` must be capable of holding the value 2
+(i.e., UXLEN=64 must be supported).
 
 ==== RVB23S64 Optional Extensions
 
@@ -265,21 +293,23 @@ RVB23S64 has the same unprivileged options as RVB23U64,
 RVB23S64 has the same six privileged options (Sv48, Sv57, Svadu,
 Sscofpmf, Zkr, H) as RVA23S64.
 
-The privileged optional extensions are:
+===== Localized Options
 
-- *Sv48* Page-Based 48-bit Virtual-Memory System.
+There are no privileged localized options in RVB23S64.
 
-- *Sv57* Page-Based 57-bit Virtual-Memory System.
+===== Development Options
 
-- *Svadu* Hardware A/D bit updates.
+There are no privileged development options in RVB23S64.
 
-- *Sscofpmf* Count Overflow and Mode-Based Filtering.
+===== Expansion Options
 
-- *Ssnpm* Pointer masking.
+The following privileged expansion options are mandatory in RVA22S64 but options in RVB23S64:
 
-- *Zkr*  Entropy CSR.
+- *Ssnpm* Pointer masking, with `senvcfg.PME` supporting at minimum,
+   settings PMLEN=0 and PMLEN=7.
 
-The following hypervisor extension and mandates were also in RVA22S64:
+The following hypervisor extension and mandates were also in RVA22S64
+and are available as an expansion option in RVB23S64:
 
 - *H* The hypervisor extension.
 
@@ -306,6 +336,33 @@ When the hypervisor extension is implemented, the following are also mandatory:
   `satp`, the corresponding hgatp SvNNx4 mode must be supported.  The
   `hgatp` mode Bare must also be supported.
 
+- If the hypervisor extension is implemented and pointer masking
+  (Ssnpm) is supported then `henvcfg.PME` must support at minimum,
+  settings PMLEN=0 and PMLEN=7.
+
+The following privileged expansion options are also present in RVA23S64:
+
+- *Sv48* Page-Based 48-bit Virtual-Memory System.
+
+- *Sv57* Page-Based 57-bit Virtual-Memory System.
+
+- *Svadu* Hardware A/D bit updates.
+
+- *Zkr*  Entropy CSR.
+
+- *Svadu* Hardware A/D bit updates.
+
+- *Sdext* Debug triggers
+
+- *Ssstrict* No non-conforming extensions are present.  Attempts to
+   execute unimplemented opcodes or access unimplemented CSRs in the
+   standard or reserved encoding spaces raises an illegal instruction
+   exception that results in a contained trap to the supervisor-mode
+   trap handler.
+
+NOTE: Ssstrict does not prescribe behavior for the custom encoding
+spaces or CSRs.
+
 ==== RVB23S64 Recommendations
 
 - Implementations are strongly recommended to raise illegal-instruction