Draft verilog generators

examples/axi-lite-rmii.yml

@@ -0,0 +1,19 @@
+#
+# This file is part of LiteEth.
+#
+# Copyright (c) 2020 Florent Kermarrec <[email protected]>
+# Copyright (c) 2022 Victor Suarez Rovere <[email protected]>
+# SPDX-License-Identifier: BSD-2-Clause
+
+# PHY ----------------------------------------------------------------------
+phy:        LiteEthPHYRMII
+vendor:     xilinx
+toolchain:  vivado
+# Core ---------------------------------------------------------------------
+clk_freq:   100e6
+core:       axi-lite
+endianness: big
+
+soc:
+    mem_map:
+        ethmac: 0x50000000

examples/axi-lite-sim.yml

@@ -0,0 +1,19 @@
+#
+# This file is part of LiteEth.
+#
+# Copyright (c) 2020 Florent Kermarrec <[email protected]>
+# Copyright (c) 2022 Victor Suarez Rovere <[email protected]>
+# SPDX-License-Identifier: BSD-2-Clause
+
+# PHY ----------------------------------------------------------------------
+phy:        LiteEthPHYModel
+vendor:     xilinx
+toolchain:  vivado
+# Core ---------------------------------------------------------------------
+clk_freq:   100e6
+core:       axi-lite
+endianness: big
+
+soc:
+    mem_map:
+        ethmac: 0x50000000

examples/etherbone_mii.yml

@@ -0,0 +1,25 @@
+#
+# This file is part of LiteEth.
+#
+# Copyright (c) 2020 Florent Kermarrec <[email protected]>
+# Copyright (c) 2022 Victor Suarez Rovere <[email protected]>
+# SPDX-License-Identifier: BSD-2-Clause
+
+# PHY ----------------------------------------------------------------------
+phy:        LiteEthPHYMII
+vendor:     xilinx
+toolchain:  vivado
+
+# Core ---------------------------------------------------------------------
+clk_freq:   100e6
+core:       etherbone
+
+#MAC & IP ------------------------------------------------------------------
+mac_address: 0x10e2d5000001
+ip_address:  "192.168.1.51"
+
+# SoC ----------------------------------------------------------------------
+soc:
+    mem_map:
+        ethmac: 0x50000000
+

examples/etherbone_sim.yml

@@ -0,0 +1,25 @@
+#
+# This file is part of LiteEth.
+#
+# Copyright (c) 2020 Florent Kermarrec <[email protected]>
+# Copyright (c) 2022 Victor Suarez Rovere <[email protected]>
+# SPDX-License-Identifier: BSD-2-Clause
+
+# PHY ----------------------------------------------------------------------
+phy:        LiteEthPHYModel
+vendor:     xilinx
+toolchain:  vivado
+
+# Core ---------------------------------------------------------------------
+clk_freq:   100e6
+core:       etherbone
+
+#MAC & IP ------------------------------------------------------------------
+mac_address: 0x10e2d5000001
+ip_address:  "192.168.1.51"
+
+# SoC ----------------------------------------------------------------------
+soc:
+    mem_map:
+        ethmac: 0x50000000
+

examples/wishbone_rmii.yml

@@ -0,0 +1,19 @@
+#
+# This file is part of LiteEth.
+#
+# Copyright (c) 2020 Florent Kermarrec <[email protected]>
+# Copyright (c) 2022 Victor Suarez Rovere <[email protected]>
+# SPDX-License-Identifier: BSD-2-Clause
+
+# PHY ----------------------------------------------------------------------
+phy:        LiteEthPHYRMII
+vendor:     xilinx
+toolchain:  vivado
+# Core ---------------------------------------------------------------------
+clk_freq:   100e6
+core:       wishbone
+endianness: big
+
+soc:
+    mem_map:
+        ethmac: 0x50000000

liteeth/gen.py

@@ -129,6 +129,21 @@
         Subsignal("tx_ctl",  Pins(1)),
         Subsignal("tx_data", Pins(4))
     ),
+
+    # Simulation model (Stream Endpoint)
+    ("sim_eth_clocks", 0,
+        Subsignal("tx", Pins(1)),
+        Subsignal("rx", Pins(1))
+    ),
+    ("sim_eth", 0,
+        Subsignal("source_valid", Pins(1)),
+        Subsignal("source_ready", Pins(1)),
+        Subsignal("source_data",  Pins(8)),
+
+        Subsignal("sink_valid",   Pins(1)),
+        Subsignal("sink_ready",   Pins(1)),
+        Subsignal("sink_data",    Pins(8)),
+    ),
 ]
 
 def get_udp_port_ios(name, data_width, dynamic_params=False):
@@ -212,6 +227,8 @@ def __init__(self, platform, core_config):
                 tx_delay           = core_config.get("phy_tx_delay", 2e-9),
                 rx_delay           = core_config.get("phy_rx_delay", 2e-9),
                 with_hw_init_reset = False) # FIXME: required since sys_clk = eth_rx_clk.
+        elif phy in [liteeth_phys.LiteEthPHYModel]:
+            ethphy = phy(self.platform.request("sim_eth", 0))
         else:
             raise ValueError("Unsupported PHY")
         self.submodules.ethphy = ethphy
@@ -228,15 +245,52 @@ def __init__(self, platform, core_config):
             self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
             self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
 
-# MAC Core -----------------------------------------------------------------------------------------
 
+    #generic function to add wishbone cores (possibly adapted to axi-lite)
+    def add_adapted_wb_master(self, wb_core, bus_standard):
+        assert bus_standard in ["wishbone", "axi-lite"]
+
+        if bus_standard == "wishbone":
+          # Wishbone Interface -----------------------------------------------------------------------
+          wb_bus = wishbone.Interface()
+          self.platform.add_extension(wb_bus.get_ios("wishbone"))
+          self.comb += wb_bus.connect_to_pads(self.platform.request("wishbone"), mode="master")
+          self.add_wb_master(wb_bus)
+
+        if bus_standard == "axi-lite":
+          # AXI-Lite Interface -----------------------------------------------------------------------
+          axil_bus = axi.AXILiteInterface(address_width=32, data_width=32)
+          self.platform.add_extension(axil_bus.get_ios("bus"))
+
+          #use AXILite2Wishbone for slaves
+          self.submodules += axi.Wishbone2AXILite(wb_core, axil_bus)
+          self.comb += axil_bus.connect_to_pads(self.platform.request("bus"), mode="master")
+          self.bus.add_master(master=axil_bus)
+
+    def add_adapted_wb_slave(self, wb_core, bus_standard): #TODO: to be tested
+        # Wishbone.
+        if bus_standard == "wishbone":
+            platform.add_extension(wb_core.get_ios("bus"))
+            platform_bus = self.platform.request("bus")
+            self.comb += wb_core.connect_to_pads(platform_bus, mode="slave")
+
+        # AXI-Lite.
+        if bus_standard == "axi-lite":
+            # core is in Wishbone, converter to AXI-Lite and expose the AXI-Lite Bus.
+            axil_bus = axi.AXILiteInterface(address_width=32, data_width=32)
+            platform.add_extension(axil_bus.get_ios("bus"))
+
+            #adapter should be Wishbone2AXILite the opposite for masters
+            self.submodules += axi.AXILite2Wishbone(axil_bus, wb_core)
+            self.comb += axil_bus.connect_to_pads(self.platform.request("bus"), mode="slave")
+
+# MAC Core -----------------------------------------------------------------------------------------
 class MACCore(PHYCore):
     def __init__(self, platform, core_config):
         # Parameters -------------------------------------------------------------------------------
         nrxslots = core_config.get("nrxslots", 2)
         ntxslots = core_config.get("ntxslots", 2)
         eth_bus_standard = core_config["core"]
-        assert eth_bus_standard in ["wishbone", "axi-lite"]
 
         # PHY --------------------------------------------------------------------------------------
         PHYCore.__init__(self, platform, core_config)
@@ -251,20 +305,7 @@ def __init__(self, platform, core_config):
             ntxslots       = ntxslots,
             full_memory_we = core_config.get("full_memory_we", False))
 
-        if eth_bus_standard == "wishbone":
-          # Wishbone Interface -----------------------------------------------------------------------
-          wb_bus = wishbone.Interface()
-          platform.add_extension(wb_bus.get_ios("wishbone"))
-          self.comb += wb_bus.connect_to_pads(self.platform.request("wishbone"), mode="slave")
-          self.add_wb_master(wb_bus)
-
-        if eth_bus_standard == "axi-lite":
-          # AXI-Lite Interface -----------------------------------------------------------------------
-          axil_bus = axi.AXILiteInterface(address_width=32, data_width=32)
-          platform.add_extension(axil_bus.get_ios("bus"))
-          self.submodules += axi.Wishbone2AXILite(ethmac.bus, axil_bus)
-          self.comb += axil_bus.connect_to_pads(self.platform.request("bus"), mode="slave")
-          self.bus.add_master(master=axil_bus)
+        self.add_adapted_wb_master(ethmac.bus, eth_bus_standard)
 
         ethmac_region_size = (nrxslots + ntxslots)*buffer_depth
         ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False)
@@ -298,7 +339,7 @@ def __init__(self, platform, core_config):
 
         # Core -------------------------------------------------------------------------------------
         data_width = core_config.get("data_width", 8)
-        self.submodules.core = LiteEthUDPIPCore(self.ethphy,
+        self.submodules.core = eth_core = LiteEthUDPIPCore(self.ethphy,
             mac_address = mac_address,
             ip_address  = ip_address,
             clk_freq    = core_config["clk_freq"],
@@ -365,6 +406,48 @@ def __init__(self, platform, core_config):
                 port_ios.source_error.eq(udp_streamer.source.error),
             ]
 
+        eth_bus_standard = core_config["core"]
+        self.add_adapted_wb_master(eth_core.bus, eth_bus_standard)
+
+
+class EtherboneCore(PHYCore):
+    def __init__(self, platform, core_config):
+
+        # Config -----------------------------------------------------------------------------------
+
+        # MAC Address.
+        mac_address = core_config.get("mac_address", None)
+        # Get MAC Address from IOs when not specified.
+        if mac_address is None:
+            mac_address = platform.request("mac_address")
+
+        # IP Address.
+        ip_address = core_config.get("ip_address", None)
+        # Get IP Address from IOs when not specified.
+        if ip_address is None:
+            ip_address = platform.request("ip_address")
+
+        # PHY --------------------------------------------------------------------------------------
+        PHYCore.__init__(self, platform, core_config)
+
+        from liteeth.core import LiteEthUDPIPCore
+        self.submodules.ethcore_etherbone = ethcore = LiteEthUDPIPCore(
+            phy         = self.ethphy,
+            mac_address = mac_address,
+            ip_address  = ip_address,
+            clk_freq    = self.clk_freq,
+            dw          = 32,
+            with_ip_broadcast = True,
+            with_sys_datapath = True,
+          )
+
+        # Etherbone
+        from liteeth.frontend.etherbone import LiteEthEtherbone
+        etherbone = LiteEthEtherbone(ethcore.udp, 1234, buffer_depth=16, cd="sys")
+        self.submodules.etherbone_etherbone = etherbone
+
+        self.add_adapted_wb_master(etherbone.wishbone.bus, "axi-lite") # or "wishbone"
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
@@ -405,6 +488,8 @@ def main():
         soc = MACCore(platform, core_config)
     elif core_config["core"] == "udp":
         soc = UDPCore(platform, core_config)
+    elif core_config["core"] == "etherbone":
+        soc = EtherboneCore(platform, core_config)
     else:
         raise ValueError("Unknown core: {}".format(core_config["core"]))
 

liteeth/phy/__init__.py

@@ -36,3 +36,5 @@ def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
 from liteeth.phy.a7_1000basex import A7_1000BASEX
 from liteeth.phy.k7_1000basex import K7_1000BASEX
 from liteeth.phy.ku_1000basex import KU_1000BASEX
+
+from liteeth.phy.model  import LiteEthPHYModel #used for simulation