Rev 9

9.0 (2024-05-06)

• FPGA V3:
  • Implemented 4-port Ethernet switch, with two ports for external RJ45 connectors (Eth1 and Eth2), one port for Zynq ARM processor (PS), and one port for real-time interface in FPGA (PL).
    • Currently supports only 1GB Ethernet connections
  • Support Ethernet-only network, via daisy-chain connection to all FPGA boards, with all protocols, including sequential-read-broadcast-write and broadcast-query-read-write
    • Uses board-id instead of FireWire node-id
    • Hub FPGA sends broadcast read response when all data ready (does not require block read from host PC)
    • Broadcast read response can have board data in any order (no longer sequential by board number)
  • Supports Ethernet/FireWire bridge, with all protocols
  • Complete interface (i.e., quadlet and block, read and write) from PS to FPGA registers via EMIO (Version 1).
  • Revised Ethernet status/control register (12)
    • Can enable/disable PS connection to Ethernet switch (initially disabled, enabled by embedded software during initialization)
• FPGA V3 and V2:
  • Board number is automatically added to lsb of IP address
  • Support UDP multicast (address 224.0.0.100), including for broadcast-write protocols
  • Send raw Ethernet multicast packets when IP address assigned (to initialize Ethernet switches) and for publishing data in broadcast-query-read-write protocol.
  • Improved arbitration between FireWire, Ethernet and Zynq EMIO (FPGA V3 only) for FPGA internal busses.
  • Separate timestamps for FireWire, Ethernet and Zynq EMIO (FPGA V3 only) interfaces
• FPGA V2:
  • Limited support for all protocols on Ethernet-only network (FPGA V2 has only one Ethernet port)
• All FPGA Versions (V1, V2, V3):
  • Added register 15, which contains build information based on git describe
  • Added reg_rwait to indicate whether read bus requires 0 or 1 wait-states when reading data
  • Design improvements, including simplification of internal busses
  • Removed xise project files; only support building with CMake and Xilinx ISE command line tools
  • Removed many obsolete files from repository, including Generated directory (use GitHub Releases instead).
• DRAC (dVRK-Si):
  • Corrected error in ECM encoder preload

Rev 8

8.0 (2023-08-10)

• Supports FPGA V3.X, which uses the Xilinx Zynq XC7Z020 and contains two Ethernet and two IEEE-1394 (Firewire) ports. There are four variations of firmware for FPGA V3.X, which support two boards in addition to the QLA:
  • FPGA1394V3-QLA: FPGA V3.X combined with Quad Linear Amplifier (QLA), which is directly compatible with the FPGA V1.X and V2.X firmware.
  • FPGA1394V3-DQLA: FPGA V3.X combined with Dual Quad Linear Amplifier (DQLA), enabling one FPGA board to drive two QLAs.
  • FPGA1394V3-DRAC: FPGA V3.X combined with dRAC for controlling the dVRK-Si PSM or ECM.
  • FPGA1394V3-BCFG: FPGA V3.X boot configuration firmware that detects which board is connected.
• Renamed FPGA1394-QLA to FPGA1394V1-QLA and FPGA1394Eth-QLA to FPGA1394V2-QLA to achieve a consistent naming convention.
• Changes to the real-time block read and write formats. As a result, the broadcast read/write protocols require that all (or no) FPGA boards have Firmware Rev 8 (i.e., cannot have mix of Rev 8 and older firmware, unless using the less efficient sequential read/write protocol):
  • Added header quadlet to real-time block write that specifies target board id and block length
  • Changed real-time block read to support different numbers of motors and encoders, which is required for dRAC
  • Added motor status register to real-time block read
• Support reading of Dallas DS2505 PROM via DS2480B driver in addition to direct 1-wire interface (Rev 7.0 supported only the 1-wire interface)
• Support QLA Rev 1.5+:
  • Can use 1 quad DAC (LTC2604) instead of 4 single DAC (LTC2601)
  • Interface to MAX7317 I/O expander on QLA, which provides capability to:
    • Enable/disable the follower OPA549 amplifier on each of the four channels
    • Switch between analog current and voltage control on each of the four channels
    • Indicate whether +12V present on safety line
    • Support measurement of motor power supply voltage
• Added bits to Status/Control Register for QLA (DQLA and dRAC use new register definitions):
  • Read whether QLA I/O expander was detected (i.e., whether QLA is Rev 1.5+)
  • Write to redetect whether QLA I/O expander present
  • Read which DAC type was detected (1xLTC2604 or 4xLTC2601)
  • Write to redetect QLA DAC type
  • Read whether +12V detected on safety line (QLA Rev 1.5+)
• Added bit to Digital Input/Output Register for determining motor power supply voltage (QLA Rev 1.5+)
• Added bits to DAC output register to enable axis and to specify control mode
  • Enabling axis through Status/Control Register deprecated for QLA (not supported for other boards)
  • Voltage control mode only supported for QLA Rev 1.5+
• Added following new registers:
  • Motor Config
  • Motor Status
• Added motor current safety check when in voltage control mode
  • Current limit specified via Motor Config register
• Added watchdog period feedback via LEDs
• Significant updates to improve modularity of source code, including:
  • Separate files for each version of FPGA (V1, V2, V3)
  • Separate files for each type of attached board (QLA, DQLA, DRAC)
  • Moved KSZ8851 interface from EthernetIO to separate file and made EthernetIO compatible with both KSZ8851 (FPGA V2.X) and RTL8211F (FPGA V3.X)
  • Consolidated motor channel code in MotorChannelQLA.v
• CMake changes:
  • Support use of XPS (platgen) for Zynq PS7 and gmii-to-rgmii IP cores
  • Use XCP files instead of XCO for coregen
  • Use CMake functions instead of macros
  • Generate mechatronics-firmware-config.cmake in build tree

NOTE: Many of the release assets (bit files) for FPGA V3 are also in mechatronics-embedded repository, in fpgav3-micro-sd.zip.

Rev 7

7.0 (2021-04-07)

• Ethernet support (for FPGA V2.X). The Ethernet port should be configured for "link local", which assigns a default address of 169.254.x.x.
  • Supports UDP and raw Ethernet frames, which get forwarded to/from the local FireWire network.
  • Implements ARP for IP address resolution
  • Supports ICMP echo (for ping).
• Changes to the real-time block read and write formats. As a result, the broadcast read/write protocols require that all (or no) FPGA boards have Firmware Rev 7 (i.e., cannot have mix of Rev 7 and older firmware, unless using the less efficient sequential read/write protocol):
  • Added power/relay control register to real-time block write, so that it does not need to be sent as a separate quadlet write.
  • Increased the number of fields in the real-time block read to improve encoder velocity estimation.
  • Changed "broadcast read" to read real-time data for active boards only, rather than always reading data for 16 boards.
  • Added extra quadlet with timing information at end of broadcast read response packet.
• Added support for 1-wire interface to Dallas DS2505. This requires the bidirectional transceivers available in QLA Rev 1.4+. When enabled, the 1-wire interface uses DOUT3 and DIR34, which is the direction control line for DOUT3/DOUT4. This interface can be used to read the instrument name from the DS2505 chip inside da Vinci instruments.
• Changed Status/Control Register bit 20, which is masked by bit 21, from "software reset" to "reboot". Setting bits 20 and 21 will cause the FPGA to reboot. This is especially useful after programming a new version of firmware.
• Initialize encoder counter to midrange (0x800000), rather than 0, to avoid possible overflow on startup.
• Changed initial watchdog period from 0xffff (341 msec) to 0x1680 (30 msec).
• Added state of IO1[8] to digital input; this FPGA input is not currently connected on the QLA.
• Implemented Configuration ROM (checked by Linux, as reported by "dmesg").
• Added real-time data collection capability.
  • Setting/clearing bit 30 on the commanded motor current (DAC value) starts/stops collection of measured motor currents on that channel, at the ADC sampling rate of ~118 kHz.
  • Data collection can only be active on one channel at a time.
  • Data collection status returned in quadlet 3 (with measured temperature) in real-time block read packet.
• Added waveform table, which allows PC to upload precisely timed waveforms to be output by any QLA digital outputs.
• Removed eth1394 bit from status register (was never used).

Rev 6

6.0 (2018-01-29)

• Improved Ethernet support (for FPGA V2.X)
• Improved efficiency of FireWire broadcast protocol by skipping boards that are on the bus, but not used by the current configuration.
• Improved timeliness of velocity estimation by measuring time between all encoder edges (e.g., A-up to A-up, A-down to A-down, B-up to B-up, B-down to B-down) and by providing additional data to enable the higher-level software to estimate acceleration from the backward difference of the last two velocities. Increased time measurement clock from 768 kHz to 3.072 MHz for better resolution and increased range from 16 bits to 22 bits (for time between encoder edges of same type).
• Corrected PWM and single-shot behaviors on digital outputs for QLA Rev 1.4+
• Added bit to status register to indicate motor voltage fault, MV-FLT (QLA Rev 1.4+)
• Clear Watchdog Timeout (bit 23) and Feedback Current Check (bits 7-4) when enabling board power or amplifier power. In prior versions of the firmware, these bits were cleared by any write command and thus could easily be missed.

Rev 5

5.0 (2016-04-27)

• There are now two versions of firmware: FPGA1394-QLA (for FPGA V1.X) and FPGA1394Eth-QLA (for FPGA V2.X, with Ethernet connector). The FPGA pin assignments are different so the firmware is not interchangeable.
• Added register for Ethernet IO and Status; most significant bit is '1' if Ethernet firmware is present; '0' otherwise.
• Reversed order of digital outputs to match schematics.
• Auto-detect whether digital output is Open Drain (MOSFET) or bi-directional transceiver.
• Added support for PWM and single-shot behaviors on digital outputs.

Rev 3

3.0 (2013-08-13)

• Changed feedback motor current check that was introduced in Rev 2
  • Disable motor power if magnitude of measured current is more than 440 mA larger than commanded current for 50 ms, except when:
    • Measured motor current is small (less than 150 mA)
    • Commanded motor current is within 440 mA of maximum value
• Added bits to status register to indicate when motor power turned off due to feedback current check (bits 7-4)
  • Bits are cleared by any write to the board, so it is possible to miss them (same is true for watchdog timeout)

Rev 2

2.0 (2013-05-29)

• Watchdog
  • Turn on watchdog by default (default watchdog is 340 ms)
  • Turn off auto re-enable amplifier (need new data to re-enable)
• Add 40 ms sleep after board power enable
• Check feedback motor current against command motor current
  • disable amplifier if current error is more than 900 mA

Rev 1

1.0 (2013-01-08)

• Initial Release (for FPGA V1)

Rev 4

4.0 (2014-03-18)

• Improved estimation of velocity from encoder feedback
• Added support for broadcast communication between PC and FPGA boards
• Added Encoder A, B, I input state to digital feedback (0x0A)
• Added 25AA128 module (PROM on QLA board): byte R/W and block R/W
• Initial support for USB virtual COM port -- echos received character
• Changed FireWire address for FPGA prom from 0xC0 to 0x2000