platforms/sipeed_tang_console.py: added pcie wake_n subsignal and pci…

…e_clkreq_n
litex-hub · Feb 19, 2025 · 73b0e93 · 73b0e93
1 parent a7e1ea3
commit 73b0e93
Showing 1 changed file with 3 additions and 2 deletions.
diff --git a/litex_boards/platforms/sipeed_tang_console.py b/litex_boards/platforms/sipeed_tang_console.py
@@ -49,9 +49,10 @@
     ),
 
     # PCI Express
+    ("pcie_clkreq_n", 0, Pins("AA14"), IOStandard("LVCMOS33")),
     ("pcie", 0,
-        Subsignal("rst_n", Pins("W11")),
-        IOStandard("LVCMOS15"),
+        Subsignal("rst_n",  Pins("W11"),  IOStandard("LVCMOS15")),
+        Subsignal("wake_n", Pins("T14"),  IOStandard("LVCMOS33")),
     ),
 
     # DDR3 SDRAM MY41J128M16JT-125