[AArch64] Reduce fuse-literals limit on Apple subtargets

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -11458,12 +11458,17 @@ bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
   if (!IsLegal && (VT == MVT::f64 || VT == MVT::f32)) {
     // The cost is actually exactly the same for mov+fmov vs. adrp+ldr;
     // however the mov+fmov sequence is always better because of the reduced
-    // cache pressure. The timings are still the same if you consider
-    // movw+movk+fmov vs. adrp+ldr (it's one instruction longer, but the
-    // movw+movk is fused). So we limit up to 2 instrdduction at most.
+    // cache pressure. Where targets allow, longer sequences may be possible.
+    // For example, movw+movk+fmov may be comparable to adrp+ldr if the
+    // movw+movk is fused.
     SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn;
     AArch64_IMM::expandMOVImm(ImmInt.getZExtValue(), VT.getSizeInBits(), Insn);
-    unsigned Limit = (OptForSize ? 1 : (Subtarget->hasFuseLiterals() ? 5 : 2));
+    assert(Insn.size() <= 4 &&
+           "Should be able to build any value with at most 4 moves");
+    unsigned Limit = (OptForSize ? 1
+                                 : (Subtarget->hasFuseLiterals()
+                                        ? Subtarget->getFuseLiteralsLimit()
+                                        : 2));
     IsLegal = Insn.size() <= Limit;
   }
 

llvm/lib/Target/AArch64/AArch64Subtarget.cpp

@@ -188,6 +188,7 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) {
     PrefetchDistance = 280;
     MinPrefetchStride = 2048;
     MaxPrefetchIterationsAhead = 3;
+    FuseLiteralsLimit = 3;
     switch (ARMProcFamily) {
     case AppleA14:
     case AppleA15:

llvm/lib/Target/AArch64/AArch64Subtarget.h

@@ -70,6 +70,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
   unsigned MaxBytesForLoopAlignment = 0;
   unsigned MinimumJumpTableEntries = 4;
   unsigned MaxJumpTableSize = 0;
+  unsigned FuseLiteralsLimit = 4;
 
   // ReserveXRegister[i] - X#i is not available as a general purpose register.
   BitVector ReserveXRegister;
@@ -254,6 +255,8 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
     return MinimumJumpTableEntries;
   }
 
+  unsigned getFuseLiteralsLimit() const { return FuseLiteralsLimit; }
+
   /// CPU has TBI (top byte of addresses is ignored during HW address
   /// translation) and OS enables it.
   bool supportsAddressTopByteIgnored() const;

llvm/test/CodeGen/AArch64/literal_pools_float_apple.ll

@@ -0,0 +1,128 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=arm64-apple-macosx -mcpu=apple-m1 < %s | FileCheck %s --check-prefix=APPLE
+
+define dso_local float @float_0mov() {
+; CHECK-LABEL: float_0mov:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmov s0, #1.00000000
+; CHECK-NEXT:    ret
+;
+; APPLE-LABEL: float_0mov:
+; APPLE:       ; %bb.0:
+; APPLE-NEXT:    fmov s0, #1.00000000
+; APPLE-NEXT:    ret
+  ret float 1.0
+}
+
+define dso_local float @float_1mov() {
+; CHECK-LABEL: float_1mov:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #2143289344 // =0x7fc00000
+; CHECK-NEXT:    fmov s0, w8
+; CHECK-NEXT:    ret
+;
+; APPLE-LABEL: float_1mov:
+; APPLE:       ; %bb.0:
+; APPLE-NEXT:    mov w8, #2143289344 ; =0x7fc00000
+; APPLE-NEXT:    fmov s0, w8
+; APPLE-NEXT:    ret
+  ret float 0x7FF8000000000000
+}
+
+define dso_local float @float_2mov() {
+; CHECK-LABEL: float_2mov:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #34952 // =0x8888
+; CHECK-NEXT:    movk w8, #32704, lsl #16
+; CHECK-NEXT:    fmov s0, w8
+; CHECK-NEXT:    ret
+;
+; APPLE-LABEL: float_2mov:
+; APPLE:       ; %bb.0:
+; APPLE-NEXT:    mov w8, #34952 ; =0x8888
+; APPLE-NEXT:    movk w8, #32704, lsl #16
+; APPLE-NEXT:    fmov s0, w8
+; APPLE-NEXT:    ret
+  ret float 0x7FF8111100000000
+}
+
+define dso_local double @double_0mov() {
+; CHECK-LABEL: double_0mov:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmov d0, #1.00000000
+; CHECK-NEXT:    ret
+;
+; APPLE-LABEL: double_0mov:
+; APPLE:       ; %bb.0:
+; APPLE-NEXT:    fmov d0, #1.00000000
+; APPLE-NEXT:    ret
+  ret double 1.0
+}
+
+define dso_local double @double_1mov() {
+; CHECK-LABEL: double_1mov:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #4096 // =0x1000
+; CHECK-NEXT:    fmov d0, x8
+; CHECK-NEXT:    ret
+;
+; APPLE-LABEL: double_1mov:
+; APPLE:       ; %bb.0:
+; APPLE-NEXT:    mov x8, #4096 ; =0x1000
+; APPLE-NEXT:    fmov d0, x8
+; APPLE-NEXT:    ret
+  ret double 0x1000
+}
+
+define dso_local double @double_2mov() {
+; CHECK-LABEL: double_2mov:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #4096 // =0x1000
+; CHECK-NEXT:    movk x8, #8192, lsl #16
+; CHECK-NEXT:    fmov d0, x8
+; CHECK-NEXT:    ret
+;
+; APPLE-LABEL: double_2mov:
+; APPLE:       ; %bb.0:
+; APPLE-NEXT:    mov x8, #4096 ; =0x1000
+; APPLE-NEXT:    movk x8, #8192, lsl #16
+; APPLE-NEXT:    fmov d0, x8
+; APPLE-NEXT:    ret
+  ret double 0x20001000
+}
+
+define dso_local double @double_3mov() {
+; CHECK-LABEL: double_3mov:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    adrp x8, .LCPI6_0
+; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI6_0]
+; CHECK-NEXT:    ret
+;
+; APPLE-LABEL: double_3mov:
+; APPLE:       ; %bb.0:
+; APPLE-NEXT:    mov x8, #4096 ; =0x1000
+; APPLE-NEXT:    movk x8, #8192, lsl #16
+; APPLE-NEXT:    movk x8, #12288, lsl #32
+; APPLE-NEXT:    fmov d0, x8
+; APPLE-NEXT:    ret
+  ret double 0x300020001000
+}
+
+define dso_local double @double_4mov() {
+; CHECK-LABEL: double_4mov:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    adrp x8, .LCPI7_0
+; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI7_0]
+; CHECK-NEXT:    ret
+;
+; APPLE-LABEL: double_4mov:
+; APPLE:       ; %bb.0:
+; APPLE-NEXT:  Lloh0:
+; APPLE-NEXT:    adrp x8, lCPI7_0@PAGE
+; APPLE-NEXT:  Lloh1:
+; APPLE-NEXT:    ldr d0, [x8, lCPI7_0@PAGEOFF]
+; APPLE-NEXT:    ret
+; APPLE-NEXT:    .loh AdrpLdr Lloh0, Lloh1
+  ret double 0x4000300020001000
+}