Adder_UVM

First foray into verification

design.sv contains the sv code for an N-bit adder.

testbench.sv contains the top level verification model.

Whole thing was run on Cadence Xcelium 20.09 using EDAPlayground.

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
LICENSE		LICENSE
README.md		README.md
adder_agent.sv		adder_agent.sv
adder_driver.sv		adder_driver.sv
adder_env.sv		adder_env.sv
adder_if.sv		adder_if.sv
adder_monitor.sv		adder_monitor.sv
adder_scoreboard.sv		adder_scoreboard.sv
adder_seq.sv		adder_seq.sv
adder_seq_item.sv		adder_seq_item.sv
adder_sequencer.sv		adder_sequencer.sv
adder_tb.sv		adder_tb.sv
adder_test_lib.sv		adder_test_lib.sv
design.sv		design.sv
dpi_func.cpp		dpi_func.cpp
run.f		run.f
testbench.sv		testbench.sv

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