Phase1 state machine instance additions code update

compiler/lib/src/main/scala/analysis/Semantics/Component.scala

@@ -132,7 +132,7 @@ case class Component(
   /** Add a port instance to the port map */
   private def updateStateMachineInstanceMap(instance: StateMachineInstance):
   Result.Result[Component] = {
-    val name = instance.getUnqualifiedName
+    val name = instance.getName
     stateMachineInstanceMap.get(name) match {
       case Some(prevInstance) =>
         val loc = instance.getLoc

compiler/lib/src/main/scala/analysis/Semantics/StateMachineInstance.scala

@@ -6,16 +6,18 @@ import fpp.compiler.util._
 /** An FPP state machine instance */
 final case class StateMachineInstance(
   aNode: Ast.Annotated[AstNode[Ast.SpecStateMachineInstance]],
-  symbol: Symbol.StateMachine
+  symbol: Symbol.StateMachine,
+  priority: Option[BigInt],
+  queueFull: Ast.QueueFull
 ) {
 
   /** Gets the location of the state machine instance*/
   def getLoc: Location = Locations.get(aNode._2.id)
 
   def getNodeId = aNode._2.id
 
-  /** Gets the unqualified name of the state machine instance */
-  def getUnqualifiedName = aNode._2.data.name
+  /** Gets the name of the state machine instance */
+  def getName = aNode._2.data.name
 
 }
 
@@ -25,7 +27,12 @@ object StateMachineInstance {
   def fromSpecStateMachine(a: Analysis, 
                            aNode: Ast.Annotated[AstNode[Ast.SpecStateMachineInstance]]
   ) : Result.Result[StateMachineInstance] = {
-    val qid = aNode._2.data.stateMachine
+    val data = aNode._2.data
+    val qid = data.stateMachine
+    val priorityNode = data.priority
+    val priority = a.getBigIntValueOpt(priorityNode)
+    val queueFull = Analysis.getQueueFull(data.queueFull)
+
     for {
       symbol <- a.useDefMap(qid.id) match {
         case symbol @ Symbol.StateMachine(_) => Right(symbol)
@@ -37,7 +44,7 @@ object StateMachineInstance {
         ))
       }
     }
-    yield StateMachineInstance(aNode, symbol)
+    yield StateMachineInstance(aNode, symbol, priority, queueFull)
   }
 
 }

compiler/lib/src/main/scala/codegen/CppWriter/ComponentCppWriter/ComponentCppWriterUtils.scala

@@ -110,6 +110,10 @@ abstract class ComponentCppWriterUtils(
   /** List of serial output ports */
   val serialOutputPorts: List[PortInstance.General] = filterSerialPorts(outputPorts)
 
+  /** List of state machine instances */
+  val stateMachineInstances: List[StateMachineInstance] =
+    component.stateMachineInstanceMap.toList.map((_, sm) => sm).sortBy(_.getName)
+
   /** List of internal port instances sorted by name */
   val internalPorts: List[PortInstance.Internal] = component.portMap.toList.map((_, p) => p match {
     case i: PortInstance.Internal => Some(i)

compiler/lib/src/main/scala/codegen/CppWriter/ComponentCppWriter/ComponentStateMachines.scala

@@ -22,20 +22,8 @@ case class ComponentStateMachines(
     guardedList (hasStateMachineInstances) (List(lcm))
   }
 
-  def getFunctionMembers: List[CppDoc.Class.Member] = {
-    lazy val member = functionClassMember(
-      Some(s"State machine base-class function for sendSignals"),
-      "stateMachineInvoke",
-      List(
-        CppDoc.Function.Param(
-            CppDoc.Type("const Fw::SMSignals&"),
-            "ev",
-            Some("The state machine signal")
-        )
-      ),
-      CppDoc.Type("void"),
-      intersperseBlankLines(
-        List(
+  def getFunctionMembers: List[CppDoc.Class.Member] = {    
+    val serializeCode = 
           lines(
             s"""|ComponentIpcSerializableBuffer msg;
                 |Fw::SerializeStatus _status = Fw::FW_SERIALIZE_OK;
@@ -58,14 +46,56 @@ case class ComponentStateMachines(
                 |FW_ASSERT(
                 |  _status == Fw::FW_SERIALIZE_OK,
                 |  static_cast<FwAssertArgType>(_status)
-                |);
-                |
-                |"""
+                |);"""
+          )
+
+
+    val switchCode = List.concat(
+      lines("const U32 smId = ev.getsmId();"),
+      wrapInSwitch(
+        "smId",
+        List.concat(
+          stateMachineInstances.flatMap(
+            smi => {
+              Line.blank ::
+              wrapInScope(
+                s"case STATE_MACHINE_${smi.getName.toUpperCase}: {",
+                List.concat(
+                  writeSendMessageLogic("msg", smi.queueFull, smi.priority),
+                  lines("break;")
+                ),
+                "}"
+              )
+            }
           ),
-          writeSendMessageLogic("msg", Ast.QueueFull.Assert, Option(1))
+          lines(
+            """|
+               |default:
+               |  FW_ASSERT(0, static_cast<FwAssertArgType>(smId));
+               |  break;
+               |"""
+          )
+
+        )
+      )
+    )
+
+    val member = functionClassMember(
+      Some(s"State machine base-class function for sendSignals"),
+      "stateMachineInvoke",
+      List(
+        CppDoc.Function.Param(
+            CppDoc.Type("const Fw::SMSignals&"),
+            "ev",
+            Some("The state machine signal")
         )
+      ),
+      CppDoc.Type("void"),
+      Line.blank :: intersperseBlankLines(
+        List(serializeCode, switchCode)
       )
     )
+
     addAccessTagAndComment(
       "PROTECTED",
       "State machine function to push signals to the input queue",

compiler/tools/fpp-check/test/state_machine_instance/ok.fpp

@@ -8,8 +8,11 @@ active component C {
 
   state machine S
 
-  state machine instance s1: M.S
-  state machine instance s2: T
-  state machine instance s3: S
+  state machine instance s1: M.S priority 1 block
+  state machine instance s2: T priority 2 drop
+  state machine instance s3: S priority 3 assert
+  state machine instance s4: S priority 3+1 block 
+  state machine instance s5: S priority 3+2 
+  state machine instance s6: S 
 
 }

compiler/tools/fpp-to-cpp/test/component/base/ActiveStateMachinesComponentAc.ref.cpp

@@ -78,6 +78,8 @@ void ActiveStateMachinesComponentBase ::
   m_stateMachine_sm2.init();
   m_stateMachine_sm3.init();
   m_stateMachine_sm4.init();
+  m_stateMachine_sm5.init();
+  m_stateMachine_sm6.init();
 
   Os::Queue::QueueStatus qStat = this->createQueue(
     queueDepth,
@@ -99,7 +101,9 @@ ActiveStateMachinesComponentBase ::
     m_stateMachine_sm1(this),
     m_stateMachine_sm2(this),
     m_stateMachine_sm3(this),
-    m_stateMachine_sm4(this)
+    m_stateMachine_sm4(this),
+    m_stateMachine_sm5(this),
+    m_stateMachine_sm6(this)
 {
 
 }
@@ -117,6 +121,7 @@ ActiveStateMachinesComponentBase ::
 void ActiveStateMachinesComponentBase ::
   stateMachineInvoke(const Fw::SMSignals& ev)
 {
+
   ComponentIpcSerializableBuffer msg;
   Fw::SerializeStatus _status = Fw::FW_SERIALIZE_OK;
 
@@ -140,14 +145,90 @@ void ActiveStateMachinesComponentBase ::
     static_cast<FwAssertArgType>(_status)
   );
 
-  // Send message
-  Os::Queue::QueueBlocking _block = Os::Queue::QUEUE_NONBLOCKING;
-  Os::Queue::QueueStatus qStatus = this->m_queue.send(msg, 1, _block);
+  const U32 smId = ev.getsmId();
+  switch (smId) {
 
-  FW_ASSERT(
-    qStatus == Os::Queue::QUEUE_OK,
-    static_cast<FwAssertArgType>(qStatus)
-  );
+    case STATE_MACHINE_SM1: {
+      // Send message
+      Os::Queue::QueueBlocking _block = Os::Queue::QUEUE_BLOCKING;
+      Os::Queue::QueueStatus qStatus = this->m_queue.send(msg, 1, _block);
+
+      FW_ASSERT(
+        qStatus == Os::Queue::QUEUE_OK,
+        static_cast<FwAssertArgType>(qStatus)
+      );
+      break;
+    }
+
+    case STATE_MACHINE_SM2: {
+      // Send message
+      Os::Queue::QueueBlocking _block = Os::Queue::QUEUE_NONBLOCKING;
+      Os::Queue::QueueStatus qStatus = this->m_queue.send(msg, 2, _block);
+
+      FW_ASSERT(
+        qStatus == Os::Queue::QUEUE_OK,
+        static_cast<FwAssertArgType>(qStatus)
+      );
+      break;
+    }
+
+    case STATE_MACHINE_SM3: {
+      // Send message
+      Os::Queue::QueueBlocking _block = Os::Queue::QUEUE_NONBLOCKING;
+      Os::Queue::QueueStatus qStatus = this->m_queue.send(msg, 3, _block);
+
+      if (qStatus == Os::Queue::QUEUE_FULL) {
+        this->incNumMsgDropped();
+        return;
+      }
+
+      FW_ASSERT(
+        qStatus == Os::Queue::QUEUE_OK,
+        static_cast<FwAssertArgType>(qStatus)
+      );
+      break;
+    }
+
+    case STATE_MACHINE_SM4: {
+      // Send message
+      Os::Queue::QueueBlocking _block = Os::Queue::QUEUE_NONBLOCKING;
+      Os::Queue::QueueStatus qStatus = this->m_queue.send(msg, 4, _block);
+
+      FW_ASSERT(
+        qStatus == Os::Queue::QUEUE_OK,
+        static_cast<FwAssertArgType>(qStatus)
+      );
+      break;
+    }
+
+    case STATE_MACHINE_SM5: {
+      // Send message
+      Os::Queue::QueueBlocking _block = Os::Queue::QUEUE_BLOCKING;
+      Os::Queue::QueueStatus qStatus = this->m_queue.send(msg, 0, _block);
+
+      FW_ASSERT(
+        qStatus == Os::Queue::QUEUE_OK,
+        static_cast<FwAssertArgType>(qStatus)
+      );
+      break;
+    }
+
+    case STATE_MACHINE_SM6: {
+      // Send message
+      Os::Queue::QueueBlocking _block = Os::Queue::QUEUE_NONBLOCKING;
+      Os::Queue::QueueStatus qStatus = this->m_queue.send(msg, 0, _block);
+
+      FW_ASSERT(
+        qStatus == Os::Queue::QUEUE_OK,
+        static_cast<FwAssertArgType>(qStatus)
+      );
+      break;
+    }
+
+    default:
+      FW_ASSERT(0, static_cast<FwAssertArgType>(smId));
+      break;
+  }
 }
 
 // ----------------------------------------------------------------------
@@ -230,6 +311,14 @@ Fw::QueuedComponentBase::MsgDispatchStatus ActiveStateMachinesComponentBase ::
           this->m_stateMachine_sm4.update(&ev);
           break;
 
+        case STATE_MACHINE_SM5:
+          this->m_stateMachine_sm5.update(&ev);
+          break;
+
+        case STATE_MACHINE_SM6:
+          this->m_stateMachine_sm6.update(&ev);
+          break;
+
       }
 
       break;

compiler/tools/fpp-to-cpp/test/component/base/ActiveStateMachinesComponentAc.ref.hpp

@@ -42,6 +42,8 @@ class ActiveStateMachinesComponentBase :
       STATE_MACHINE_SM2,
       STATE_MACHINE_SM3,
       STATE_MACHINE_SM4,
+      STATE_MACHINE_SM5,
+      STATE_MACHINE_SM6,
     };
 
   public:
@@ -108,6 +110,12 @@ class ActiveStateMachinesComponentBase :
     //! State machine sm4
     ActiveStateMachines_S2 m_stateMachine_sm4;
 
+    //! State machine sm5
+    ActiveStateMachines_S2 m_stateMachine_sm5;
+
+    //! State machine sm6
+    ActiveStateMachines_S2 m_stateMachine_sm6;
+
 };
 
 #endif

compiler/tools/fpp-to-cpp/test/component/include/state_machines.fppi

@@ -11,14 +11,20 @@ state machine S2
 # ----------------------------------------------------------------------
 
 @ state machine sm1
-state machine instance sm1: S1
+state machine instance sm1: S1 priority 1 block
 
 @ state machine sm2
-state machine instance sm2: S1
+state machine instance sm2: S1 priority 2 assert
 
 @ state machine sm3
-state machine instance sm3: S2
+state machine instance sm3: S2 priority 2+1 drop
 
 @ state machine sm4
-state machine instance sm4: S2
+state machine instance sm4: S2 priority 5-1
+
+@ state machine sm5
+state machine instance sm5: S2 block 
+
+@ state machine sm6
+state machine instance sm6: S2
 

compiler/tools/fpp-to-json/test/activeComponents.ref.txt

@@ -1284,6 +1284,12 @@
             "node" : {
               "astNodeId" : 52
             }
+          },
+          "priority" : "None",
+          "queueFull" : {
+            "Assert" : {
+
+            }
           }
         },
         "s2" : {
@@ -1294,6 +1300,12 @@
             "node" : {
               "astNodeId" : 52
             }
+          },
+          "priority" : "None",
+          "queueFull" : {
+            "Assert" : {
+
+            }
           }
         }
       },