Merge pull request #456 from silabs-halfdan/rvfi_bugfix

RVFI bugfixes

Author: Silabs-ArjanB

bhv/cv32e40x_rvfi.sv

@@ -52,6 +52,8 @@ module cv32e40x_rvfi
 
    //// EX probes ////
    input logic                                branch_in_ex_i,
+   input logic                                branch_decision_ex_i,
+   input logic                                dret_in_ex_i,
    // LSU
    input logic                                lsu_en_ex_i,
    input logic                                lsu_pmp_err_ex_i,
@@ -465,6 +467,8 @@ module cv32e40x_rvfi
   logic [31:0]       ex_mem_wdata;
   mem_err_t [3:0]    mem_err;
 
+  logic              branch_taken_ex;
+
   logic [ 3:0] rvfi_mem_mask_int;
   logic [31:0] rvfi_mem_rdata_d;
   logic [31:0] rvfi_mem_wdata_d;
@@ -517,6 +521,7 @@ module cv32e40x_rvfi
   logic         pc_mux_debug;
   logic         pc_mux_dret;
   logic         pc_mux_exception;
+  logic         pc_mux_debug_exception;
   logic         pc_mux_interrupt;
   logic         pc_mux_nmi;
 
@@ -543,11 +548,18 @@ module cv32e40x_rvfi
   // The pc_mux signals probe the MUX in the IF stage to extract information about events in the WB stage.
   // These signals are therefore used both in the WB stage to see effects of the executed instruction (e.g. rvfi_trap), and
   // in the IF stage to see the reason for executing the instruction (e.g. rvfi_intr).
-  assign pc_mux_interrupt = (ctrl_fsm_i.pc_mux == PC_TRAP_IRQ);
-  assign pc_mux_nmi       = (ctrl_fsm_i.pc_mux == PC_TRAP_NMI);
-  assign pc_mux_debug     = (ctrl_fsm_i.pc_mux == PC_TRAP_DBD);
-  assign pc_mux_exception = (ctrl_fsm_i.pc_mux == PC_TRAP_EXC) || (ctrl_fsm_i.pc_mux == PC_TRAP_DBE);
-  assign pc_mux_dret      = (ctrl_fsm_i.pc_mux == PC_DRET);
+  assign pc_mux_interrupt       = (ctrl_fsm_i.pc_mux == PC_TRAP_IRQ);
+  assign pc_mux_nmi             = (ctrl_fsm_i.pc_mux == PC_TRAP_NMI);
+  assign pc_mux_debug           = (ctrl_fsm_i.pc_mux == PC_TRAP_DBD);
+  assign pc_mux_exception       = (ctrl_fsm_i.pc_mux == PC_TRAP_EXC) || pc_mux_debug_exception ;
+  // The debug exception for mret is taken in ID (contrary to all other exceptions). In the case where we have a dret in the EX stage at the same time,
+  // this can lead to a situation we take the exception for the mret even though it never reaches the WB stage.
+  // This works in rtl because the exception handler instructions will get killed.
+  // In rvfi this exception needs to be ignored as it comes from an instruction that does not retire.
+  assign pc_mux_debug_exception = (ctrl_fsm_i.pc_mux == PC_TRAP_DBE) && !dret_in_ex_i;
+  assign pc_mux_dret            = (ctrl_fsm_i.pc_mux == PC_DRET);
+
+  assign branch_taken_ex = branch_in_ex_i && branch_decision_ex_i;
 
   // Assign rvfi channels
   assign rvfi_halt = 1'b0; // No intruction causing halt in cv32e40x
@@ -733,7 +745,7 @@ module cv32e40x_rvfi
       //// EX Stage ////
       if (ex_valid_i && wb_ready_i) begin
         // Predicting branch target explicitly to avoid predicting asynchronous events
-        pc_wdata   [STAGE_WB] <= branch_in_ex_i ? branch_target_ex_i : pc_wdata[STAGE_EX];
+        pc_wdata   [STAGE_WB] <= branch_taken_ex ? branch_target_ex_i : pc_wdata[STAGE_EX];
         debug_mode [STAGE_WB] <= debug_mode         [STAGE_EX];
         debug_cause[STAGE_WB] <= debug_cause        [STAGE_EX];
         instr_pmp_err[STAGE_WB] <= instr_pmp_err    [STAGE_EX];

bhv/cv32e40x_wrapper.sv

@@ -386,6 +386,8 @@ module cv32e40x_wrapper
          .lsu_we_id_i              ( core_i.id_stage_i.lsu_we                                             ),
 
          .branch_in_ex_i           ( core_i.controller_i.controller_fsm_i.branch_in_ex                    ),
+         .branch_decision_ex_i     ( core_i.ex_stage_i.branch_decision_o                                  ),
+         .dret_in_ex_i             ( core_i.ex_stage_i.id_ex_pipe_i.sys_dret_insn                         ),
          .lsu_en_ex_i              ( core_i.ex_stage_i.id_ex_pipe_i.lsu_en                                ),
 
          .instr_pmp_err_if_i       ( 1'b0                          /* PMP not implemented in cv32e40x */  ),

rtl/cv32e40x_load_store_unit.sv

@@ -267,7 +267,7 @@ module cv32e40x_load_store_unit import cv32e40x_pkg::*;
 
   logic [31:0] rdata_ext;
   logic [63:0] rdata_full;
-  logic [31:0] rdata_aligned;
+  logic [63:0] rdata_aligned; // [63:32] unsused
   logic        rdata_is_split;
 
   // Check if rdata is split over two accesses