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Implement CLIC spec chapter 8.4 - Exception handling #499

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silabs-oysteink opened this issue Apr 6, 2022 · 1 comment
Closed

Implement CLIC spec chapter 8.4 - Exception handling #499

silabs-oysteink opened this issue Apr 6, 2022 · 1 comment

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@silabs-oysteink
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The spec states:

"Horizontal synchronous exception traps, which stay within a privilege mode, are serviced with the same interrupt
level as the instruction that raised the exception.
Vertical synchronous exception traps, which are serviced at a higher privilege mode, are taken at interrupt level 0
in the higher privilege mode."

This is not yet currently implemented.
silabs-oysteink added a commit to silabs-oysteink/cv32e40x that referenced this issue Aug 30, 2022
@silabs-oysteink
Fix for issue openhwgroup#499.
16f3f1b 
Horizontal traps (exceptions) to the same privilege level will now keep the value in mintstatus.mil stable. Previously this was updated to whatever value was on ctrl_fsm.irq_level regardless of exceptions or interrupts being taken.

Signed-off-by: Oystein Knauserud <[email protected]>
silabs-oysteink added a commit that referenced this issue Sep 1, 2022
@silabs-oysteink
Merge pull request #659 from silabs-oysteink/silabs-oysteink_issue-499
e7431ad 
Fix for issue #499.
@silabs-oysteink
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Shoudl be fixed with PR #659, closing issue.

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