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rvfi_trap fixes #365

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Jan 3, 2022
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rvfi_trap fixes #365

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76 changes: 37 additions & 39 deletions docs/user_manual/source/rvfi.rst
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Expand Up @@ -72,9 +72,9 @@ The trap signal indicates that a synchronous trap has ocurred and side-effects c

.. code-block:: verilog

output [NRET * 12 - 1 : 0] rvfi_trap
output [NRET * 14 - 1 : 0] rvfi_trap

``rvfi_trap`` consists of 12 bits.
``rvfi_trap`` consists of 14 bits.
``rvfi_trap[0]`` is asserted if an instruction causes an exception or debug entry.
``rvfi_trap[2:1]`` indicate trap type. ``rvfi_trap[1]`` is set for synchronous traps that do not cause debug entry. ``rvfi_trap[2]`` is set for synchronous traps that do cause debug mode entry.
``rvfi_trap[8:3]`` provide information about non-debug traps, while ``rvfi_trap[11:9]`` provide information about traps causing entry to debug mode.
Expand All @@ -86,43 +86,41 @@ The different trap scenarios, their expected side-effects and trap signalling ar
.. table:: Table of synchronous trap types
:name: Table of synchronous trap types

+------------------------------+-----------+--------------------------------------------+-----------------+-----------------------------------------------------------------------+
| Scenario | Trap Type | rvfi_trap | CSRs updated | Description |
| | +-----+-----+-----+-------+--------+---------+ | |
| | | [0] | [1] | [2] | [8:3] | [11:9] | [13:12] | | |
+==============================+===========+=====+=====+=====+=======+========+=========+=================+=======================================================================+
| Instruction Access Fault | Exception | 1 | 1 | X | 0x1 | X | 0x0 | mcause, mepc | PMA detects instruction execution from non-executable memory |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+-----------------+-----------------------------------------------------------------------+
| Illegal Instruction | Exception | 1 | 1 | X | 0x2 | X | 0x0 | mcause, mepc | Illegal instruction decode |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+-----------------+-----------------------------------------------------------------------+
| Breakpoint | Exception | 1 | 1 | X | 0x3 | X | 0x0 | mcause, mepc | EBREAK executed with dcsr.ebreakm == 0 |
| | | | | | | +---------+-----------------+-----------------------------------------------------------------------+
| | | | | | | | 0x1 | mcause, mepc | Instruction address breakpoint (trigger match, timing=0, action=0) |
| | | | | | | +---------+-----------------+-----------------------------------------------------------------------+
| | | | | | | | 0x2 | mcause, mepc | Load/store/AMO address breakpoint (trigger match, timing=0, action=0) |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+-----------------+-----------------------------------------------------------------------+
| Load Access Fault | Exception | 1 | 1 | X | 0x5 | X | 0x0 | mcause, mepc | Non-naturally aligned load access attempt to an I/O region. |
| | | | | | | +---------+-----------------+-----------------------------------------------------------------------+
| | | | | | | | 0x1 | mcause, mepc | Load-Reserved attempt to region without atomic support. |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+-----------------+-----------------------------------------------------------------------+
| Store/AMO Access Fault | Exception | 1 | 1 | X | 0x7 | X | 0x0 | mcause, mepc | Non-naturally aligned store access attempt to an I/O region |
| | | | | | | +---------+-----------------+-----------------------------------------------------------------------+
| | | | | | | | 0x1 | mcause, mepc | SC or AMO attempt to region without atomic support. |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+-----------------+-----------------------------------------------------------------------+
| Environment Call | Exception | 1 | 1 | X | 0x0B | X | 0x0 | mcause, mepc | ECALL executed |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+-----------------+-----------------------------------------------------------------------+
| Instruction Bus Fault | Exception | 1 | 1 | X | 0x30 | X | 0x0 | mcause, mepc | OBI bus error on instruction fetch |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+-----------------+-----------------------------------------------------------------------+
| Breakpoint to debug | Debug | 1 | X | 1 | X | 0x1 | 0x0 | dpc, dcsr | EBREAK from non-debug mode executed with dcsr.ebreakm == 1 |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+-----------------+-----------------------------------------------------------------------+
| Breakpoint in debug | Debug | 1 | X | 1 | X | 0x1 | 0x0 | No CSRs updated | EBREAK in debug mode jumps to debug handler |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+-----------------+-----------------------------------------------------------------------+
| Debug Trigger Match | Debug | 1 | X | 1 | X | 0x2 | 0x0 | dpc, dcsr | Debug trigger address match, instruction is not executed. |
| (timing=0) | | | | | | | | | Timing parameter is forced to 0 for cv32e4* cores. |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+-----------------+-----------------------------------------------------------------------+
| Single step | Debug | 1 | X | 1 | X | 0x4 | 0x0 | dpc, dcsr | Single step |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+-----------------+-----------------------------------------------------------------------+

+------------------------------+-----------+--------------------------------------------+----------------------+------------------------------------------------------------------------------------------------------+
| Scenario | Trap Type | rvfi_trap | CSRs updated | Description |
| | +-----+-----+-----+-------+--------+---------+ | |
| | | [0] | [1] | [2] | [8:3] | [11:9] | [13:12] | | |
+==============================+===========+=====+=====+=====+=======+========+=========+======================+======================================================================================================+
| Instruction Access Fault | Exception | 1 | 1 | X | 0x01 | X | 0x0 | ``mcause``, ``mepc`` | PMA detects instruction execution from non-executable memory. |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+----------------------+------------------------------------------------------------------------------------------------------+
| Illegal Instruction | Exception | 1 | 1 | X | 0x02 | X | 0x0 | ``mcause``, ``mepc`` | Illegal instruction decode. |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+----------------------+------------------------------------------------------------------------------------------------------+
| Breakpoint | Exception | 1 | 1 | X | 0x03 | X | 0x0 | ``mcause``, ``mepc`` | EBREAK executed with ``dcsr.ebreakm`` = 0. |
| | | | | | | +---------+----------------------+------------------------------------------------------------------------------------------------------+
| | | | | | | | 0x1 | ``mcause``, ``mepc`` | Instruction address breakpoint (trigger match, ``mcontrol.timing`` = 0, ``mcontrol.action`` = 0). |
| | | | | | | +---------+----------------------+------------------------------------------------------------------------------------------------------+
| | | | | | | | 0x2 | ``mcause``, ``mepc`` | Load/store/AMO address breakpoint (trigger match, ``mcontrol.timing`` = 0, ``mcontrol.action`` = 0). |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+----------------------+------------------------------------------------------------------------------------------------------+
| Load Access Fault | Exception | 1 | 1 | X | 0x05 | X | 0x0 | ``mcause``, ``mepc`` | Non-naturally aligned load access attempt to an I/O region. |
| | | | | | | +---------+----------------------+------------------------------------------------------------------------------------------------------+
| | | | | | | | 0x1 | ``mcause``, ``mepc`` | Load-Reserved attempt to region without atomic support. |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+----------------------+------------------------------------------------------------------------------------------------------+
| Store/AMO Access Fault | Exception | 1 | 1 | X | 0x07 | X | 0x0 | ``mcause``, ``mepc`` | Non-naturally aligned store access attempt to an I/O region. |
| | | | | | | +---------+----------------------+------------------------------------------------------------------------------------------------------+
| | | | | | | | 0x1 | ``mcause``, ``mepc`` | SC or AMO attempt to region without atomic support. |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+----------------------+------------------------------------------------------------------------------------------------------+
| Environment Call | Exception | 1 | 1 | X | 0x0B | X | 0x0 | ``mcause``, ``mepc`` | ECALL executed from Machine mode. |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+----------------------+------------------------------------------------------------------------------------------------------+
| Instruction Bus Fault | Exception | 1 | 1 | X | 0x30 | X | 0x0 | ``mcause``, ``mepc`` | OBI bus error on instruction fetch. |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+----------------------+------------------------------------------------------------------------------------------------------+
| Breakpoint to debug | Debug | 1 | 0 | 1 | X | 0x1 | 0x0 | ``dpc``, ``dcsr`` | EBREAK from non-debug mode executed with ``dcsr.ebreakm`` == 1. |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+----------------------+------------------------------------------------------------------------------------------------------+
| Breakpoint in debug | Debug | 1 | 0 | 1 | X | 0x1 | 0x0 | No CSRs updated | EBREAK in debug mode jumps to debug handler. |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+----------------------+------------------------------------------------------------------------------------------------------+
| Debug Trigger Match | Debug | 1 | 0 | 1 | X | 0x2 | 0x0 | ``dpc``, ``dcsr`` | Debug trigger address match with ``mcontrol.timing`` = 0. |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+----------------------+------------------------------------------------------------------------------------------------------+
| Single step | Debug | 1 | X | 1 | X | 0x4 | X | ``dpc``, ``dcsr`` | Single step. |
+------------------------------+-----------+-----+-----+-----+-------+--------+---------+----------------------+------------------------------------------------------------------------------------------------------+

**Interrupts**

Expand Down