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Update MPU to support data access in instruction side. In preparation… #450

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Feb 22, 2022
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1 change: 1 addition & 0 deletions rtl/cv32e40x_if_stage.sv
Original file line number Diff line number Diff line change
Expand Up @@ -186,6 +186,7 @@ module cv32e40x_if_stage import cv32e40x_pkg::*;
// Misaligned access to main is allowed, and accesses outside main will
// result in instruction access fault (which will have priority over
// misaligned from I/O fault)
.if_data_access_i ( 1'b0 ), // Indicate data access from IF stage. TODO: Use for table jumps and CLIC hardware vectoring
.core_one_txn_pend_n ( prefetch_one_txn_pend_n ),
.core_trans_valid_i ( prefetch_trans_valid ),
.core_trans_ready_o ( prefetch_trans_ready ),
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1 change: 1 addition & 0 deletions rtl/cv32e40x_load_store_unit.sv
Original file line number Diff line number Diff line change
Expand Up @@ -538,6 +538,7 @@ module cv32e40x_load_store_unit import cv32e40x_pkg::*;
.rst_n ( rst_n ),
.atomic_access_i ( 1'b0 ), // TODO:OE update to support atomic PMA checks
.misaligned_access_i ( misaligned_access ),
.if_data_access_i ( 1'b0 ), // Only applicable for IF stage

.core_one_txn_pend_n ( cnt_is_one_next ),
.core_trans_valid_i ( trans_valid ),
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5 changes: 3 additions & 2 deletions rtl/cv32e40x_mpu.sv
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@ module cv32e40x_mpu import cv32e40x_pkg::*;

input logic atomic_access_i, // Indicate that ongoing access is atomic
input logic misaligned_access_i, // Indicate that ongoing access is part of a misaligned access
input logic if_data_access_i, // Indicate that ongoing access is a data access from the IF stage

// Interface towards bus interface
input logic bus_trans_ready_i,
Expand Down Expand Up @@ -190,8 +191,8 @@ module cv32e40x_mpu import cv32e40x_pkg::*;
// Tie to 1'b0 if this MPU is instantiatied in the IF stage
generate
if (IF_STAGE) begin: mpu_if
assign instr_fetch_access = 1'b1;
assign load_access = 1'b0;
assign instr_fetch_access = if_data_access_i ? 1'b0 : 1'b1;
assign load_access = if_data_access_i ? 1'b1 : 1'b0;
assign core_trans_we = 1'b0;
end
else begin: mpu_lsu
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