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Fixed mpie R/W attribute #481

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merged 2 commits into from
Mar 23, 2022
Merged

Fixed mpie R/W attribute #481

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17fc200
Fixed mpie R/W attribute
Silabs-ArjanB Mar 23, 2022
4cdfb99
Fixed table title and table description
Silabs-ArjanB Mar 23, 2022
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10 changes: 5 additions & 5 deletions docs/user_manual/source/control_status_registers.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -196,13 +196,13 @@ instruction exception.

.. only:: USER

.. table:: Control and Status Register Map (additional CSRs for User mode)
:name: Control and Status Register Map (additional CSRs for User mode)
.. table:: Control and Status Register Map (additional CSRs for User mode support)
:name: Control and Status Register Map (additional CSRs for User mode support)

+-------------------+----------------+------------+------------+----------------------------------------------------+
| CSR address | Name | Privilege | Parameter | Description |
+-------------------+----------------+------------+------------+----------------------------------------------------+
| User CSRs |
| Machine CSRs |
+===================+================+============+============+====================================================+
| 0x306 | ``mcounteren`` | MRW | | Machine Counter Enable |
+-------------------+----------------+------------+------------+----------------------------------------------------+
Expand Down Expand Up @@ -422,7 +422,7 @@ Reset Value: defined (based on `X_EXT``, ``X_ECS_XS``)
+-------------+-----------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| 8 | WARL (0x0) | **SPP**. Hardwired to 0. |
+-------------+-----------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| 7 | R | **MPIE**: When an exception is encountered, MPIE will be set to MIE. When the mret instruction is executed, the value of MPIE will be stored to MIE. |
| 7 | RW | **MPIE**: When an exception is encountered, MPIE will be set to MIE. When the mret instruction is executed, the value of MPIE will be stored to MIE. |
+-------------+-----------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| 6 | WARL (0x0) | **UBE**. Hardwired to 0. |
+-------------+-----------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Expand Down Expand Up @@ -875,7 +875,7 @@ Reset Value: 0x0000_0000
+-------------+------------+----------------------------------------------------------------------------------+
| 29:28 | WARL (0x3) | **MPP:** Previous privilege mode. Same as ``mstatus.MPP`` |
+-------------+------------+----------------------------------------------------------------------------------+
| 27 | R | **MPIE:** Previous interrupt enable. Same as ``mstatus.MPIE`` |
| 27 | RW | **MPIE:** Previous interrupt enable. Same as ``mstatus.MPIE`` |
+-------------+------------+----------------------------------------------------------------------------------+
| 26:24 | RW | Reserved. Hardwired to 0. |
+-------------+------------+----------------------------------------------------------------------------------+
Expand Down