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Decoder interface change #513

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merged 1 commit into from
Apr 20, 2022
Merged

Decoder interface change #513

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48 changes: 26 additions & 22 deletions rtl/cv32e40x_decoder.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -46,8 +46,7 @@ module cv32e40x_decoder import cv32e40x_pkg::*;
output logic sys_fencei_insn_o, // fence.i instruction

// from IF/ID pipeline
input logic [31:0] instr_rdata_i, // Instruction
input logic illegal_c_insn_i, // Compressed instruction illegal
input if_id_pipe_t if_id_pipe_i,

// ALU signals
output logic alu_en_o, // ALU enable
Expand All @@ -63,7 +62,7 @@ module cv32e40x_decoder import cv32e40x_pkg::*;
output mul_opcode_e mul_operator_o, // Multiplication operation selection
output logic mul_en_o, // Perform integer multiplication
output logic [1:0] mul_signed_mode_o, // Multiplication in signed mode

// DIV related control signals
output div_opcode_e div_operator_o, // Division operation selection
output logic div_en_o, // Perform division
Expand Down Expand Up @@ -102,21 +101,26 @@ module cv32e40x_decoder import cv32e40x_pkg::*;
logic div_en;
logic sys_en;

logic [31:0] instr_rdata;

decoder_ctrl_t decoder_i_ctrl;
decoder_ctrl_t decoder_m_ctrl;
decoder_ctrl_t decoder_a_ctrl;
decoder_ctrl_t decoder_b_ctrl;
decoder_ctrl_t decoder_ctrl_mux_subdec;
decoder_ctrl_t decoder_ctrl_mux;

assign instr_rdata = if_id_pipe_i.use_merged_dec ? {16'b0, if_id_pipe_i.compressed_instr} :
if_id_pipe_i.instr.bus_resp.rdata; // todo: temporary hack while merging decoder

// RV32I Base instruction set decoder
cv32e40x_i_decoder
#(
.DEBUG_TRIGGER_EN (DEBUG_TRIGGER_EN)
)
i_decoder_i
(
.instr_rdata_i ( instr_rdata_i ),
.instr_rdata_i ( instr_rdata ),
.ctrl_fsm_i ( ctrl_fsm_i ),
.decoder_ctrl_o ( decoder_i_ctrl )
);
Expand All @@ -127,7 +131,7 @@ module cv32e40x_decoder import cv32e40x_pkg::*;
// RV32A extension decoder
cv32e40x_a_decoder a_decoder_i
(
.instr_rdata_i ( instr_rdata_i ),
.instr_rdata_i ( instr_rdata ),
.decoder_ctrl_o ( decoder_a_ctrl )
);
end else begin: no_a_decoder
Expand All @@ -142,7 +146,7 @@ module cv32e40x_decoder import cv32e40x_pkg::*;
)
b_decoder_i
(
.instr_rdata_i ( instr_rdata_i ),
.instr_rdata_i ( instr_rdata ),
.decoder_ctrl_o ( decoder_b_ctrl )
);
end else begin: no_b_decoder
Expand All @@ -157,15 +161,15 @@ module cv32e40x_decoder import cv32e40x_pkg::*;
)
m_decoder_i
(
.instr_rdata_i ( instr_rdata_i ),
.instr_rdata_i ( instr_rdata ),
.decoder_ctrl_o ( decoder_m_ctrl )
);
end else begin: no_m_decoder
assign decoder_m_ctrl = DECODER_CTRL_ILLEGAL_INSN;
end

endgenerate

// Mux control outputs from decoders
always_comb
begin
Expand All @@ -180,7 +184,7 @@ module cv32e40x_decoder import cv32e40x_pkg::*;

// Take illegal compressed instruction into account
always_comb begin
if (illegal_c_insn_i) begin
if (if_id_pipe_i.illegal_c_insn) begin
decoder_ctrl_mux = DECODER_CTRL_ILLEGAL_INSN;
end
else begin
Expand All @@ -192,27 +196,27 @@ module cv32e40x_decoder import cv32e40x_pkg::*;
assign alu_bch_o = decoder_ctrl_mux.alu_bch;
assign alu_jmp_o = decoder_ctrl_mux.alu_jmp;
assign alu_jmpr_o = decoder_ctrl_mux.alu_jmpr;
assign alu_operator_o = decoder_ctrl_mux.alu_operator;
assign alu_op_a_mux_sel_o = decoder_ctrl_mux.alu_op_a_mux_sel;
assign alu_op_b_mux_sel_o = decoder_ctrl_mux.alu_op_b_mux_sel;
assign alu_operator_o = decoder_ctrl_mux.alu_operator;
assign alu_op_a_mux_sel_o = decoder_ctrl_mux.alu_op_a_mux_sel;
assign alu_op_b_mux_sel_o = decoder_ctrl_mux.alu_op_b_mux_sel;
assign op_c_mux_sel_o = decoder_ctrl_mux.op_c_mux_sel;
assign imm_a_mux_sel_o = decoder_ctrl_mux.imm_a_mux_sel;
assign imm_b_mux_sel_o = decoder_ctrl_mux.imm_b_mux_sel;
assign imm_a_mux_sel_o = decoder_ctrl_mux.imm_a_mux_sel;
assign imm_b_mux_sel_o = decoder_ctrl_mux.imm_b_mux_sel;
assign bch_jmp_mux_sel_o = decoder_ctrl_mux.bch_jmp_mux_sel;
assign mul_en = decoder_ctrl_mux.mul_en;
assign mul_operator_o = decoder_ctrl_mux.mul_operator;
assign mul_operator_o = decoder_ctrl_mux.mul_operator;
assign mul_signed_mode_o = decoder_ctrl_mux.mul_signed_mode;
assign div_en = decoder_ctrl_mux.div_en;
assign div_operator_o = decoder_ctrl_mux.div_operator;
assign rf_re_o = decoder_ctrl_mux.rf_re;
assign rf_we = decoder_ctrl_mux.rf_we;
assign rf_re_o = decoder_ctrl_mux.rf_re;
assign rf_we = decoder_ctrl_mux.rf_we;
assign csr_en = decoder_ctrl_mux.csr_en;
assign csr_op_o = decoder_ctrl_mux.csr_op;
assign lsu_en = decoder_ctrl_mux.lsu_en;
assign lsu_we_o = decoder_ctrl_mux.lsu_we;
assign lsu_size_o = decoder_ctrl_mux.lsu_size;
assign lsu_en = decoder_ctrl_mux.lsu_en;
assign lsu_we_o = decoder_ctrl_mux.lsu_we;
assign lsu_size_o = decoder_ctrl_mux.lsu_size;
assign lsu_sext_o = decoder_ctrl_mux.lsu_sext;
assign lsu_atop_o = decoder_ctrl_mux.lsu_atop;
assign lsu_atop_o = decoder_ctrl_mux.lsu_atop;
assign sys_en = decoder_ctrl_mux.sys_en;
assign sys_mret_insn_o = decoder_ctrl_mux.sys_mret_insn;
assign sys_dret_insn_o = decoder_ctrl_mux.sys_dret_insn;
Expand All @@ -235,5 +239,5 @@ module cv32e40x_decoder import cv32e40x_pkg::*;
assign illegal_insn_o = deassert_we_i ? 1'b0 : decoder_ctrl_mux.illegal_insn;

assign alu_en_raw_o = alu_en;

endmodule // cv32e40x_decoder
6 changes: 1 addition & 5 deletions rtl/cv32e40x_id_stage.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -389,9 +389,6 @@ module cv32e40x_id_stage import cv32e40x_pkg::*;
// //
///////////////////////////////////////////////

logic [31:0] instr_merged;
assign instr_merged = if_id_pipe_i.use_merged_dec ? {16'b0, c_instr} : instr; // todo: temporary hack while merging decoder

cv32e40x_decoder
#(
.A_EXT ( A_EXT ),
Expand All @@ -415,8 +412,7 @@ module cv32e40x_id_stage import cv32e40x_pkg::*;
.sys_fencei_insn_o ( sys_fencei_insn ),

// from IF/ID pipeline
.instr_rdata_i ( instr_merged ), // todo: temporary hack while merging decoders
.illegal_c_insn_i ( if_id_pipe_i.illegal_c_insn ),
.if_id_pipe_i ( if_id_pipe_i ),

// ALU
.alu_en_o ( alu_en ),
Expand Down
6 changes: 3 additions & 3 deletions sva/cv32e40x_decoder_sva.sv
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Expand Up @@ -37,7 +37,7 @@ module cv32e40x_decoder_sva
input decoder_ctrl_t decoder_i_ctrl,
input decoder_ctrl_t decoder_b_ctrl,
input decoder_ctrl_t decoder_ctrl_mux,
input logic [31:0] instr_rdata_i,
input logic [31:0] instr_rdata,
input if_id_pipe_t if_id_pipe
);

Expand All @@ -58,7 +58,7 @@ module cv32e40x_decoder_sva
// Exclude CLIC pointers
property p_uncompressed_lsb;
@(posedge clk) disable iff(!rst_n)
!if_id_pipe.instr_meta.clic_ptr |-> (instr_rdata_i[1:0] == 2'b11);
!if_id_pipe.instr_meta.clic_ptr |-> (instr_rdata[1:0] == 2'b11);
endproperty


Expand All @@ -69,7 +69,7 @@ module cv32e40x_decoder_sva
// Check that A extension opcodes are decoded as illegal when A extension not enabled
a_illegal_0 :
assert property (@(posedge clk) disable iff (!rst_n)
(instr_rdata_i[6:0] == OPCODE_AMO) |-> (decoder_ctrl_mux.illegal_insn == 'b1))
(instr_rdata[6:0] == OPCODE_AMO) |-> (decoder_ctrl_mux.illegal_insn == 'b1))
else `uvm_error("decoder", "AMO instruction should be illegal")
end
endgenerate
Expand Down