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Typos, style #582

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Jun 14, 2022
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Typos, style #582

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25 changes: 12 additions & 13 deletions docs/user_manual/source/control_status_registers.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -1458,8 +1458,8 @@ value of the **type** field. See [RISC-V-DEBUG]_ for details regarding all trigg
+-------+-------------+----------------------------------------------------------------+
| Bit# | R/W | Description |
+=======+=============+================================================================+
| 31:28 | WARL | **type:** 6 = Address match trigger type. |
| | (0x5, 0x6) | 5 = Exception trigger |
| 31:28 | WARL (0x5, | **TYPE**. 5 = Exception trigger, 6 = Address match trigger |
| | 0x6) | type. |
+-------+-------------+----------------------------------------------------------------+
| 27 | WARL (0x1) | **DMODE**. Only debug mode can write tdata registers |
+-------+-------------+----------------------------------------------------------------+
Expand Down Expand Up @@ -1507,17 +1507,16 @@ Accessible in Debug Mode or M-Mode, depending on **tdata1.dmode**.
+-------+-------------+----------------------------------------------------------------+
| 11 | WARL (0x0) | **CHAIN**. Hardwired to 0. |
+-------+-------------+----------------------------------------------------------------+
| 10:7 | WARL | **MATCH**. 0: Address matches `tdata2`. |
| | (0x0, 0x2, | 2: Address is greater than or equal to `tdata2` |
| | 0x3) | 3: Address is less than `tdata2` |
| 10:7 | WARL (0x0, | **MATCH**. 0: Address matches `tdata2`, 2: Address is greater |
| | 0x2, 0x3) | than or equal to `tdata2`, 3: Address is less than `tdata2`. |
+-------+-------------+----------------------------------------------------------------+
| 6 | WARL | **M**. Match in M-Mode. |
+-------+-------------+----------------------------------------------------------------+
| 5 | WARL (0x0) | Hardwired to 0. |
+-------+-------------+----------------------------------------------------------------+
| 4 | WARL (0x0) | **S**. Hardwired to 0. |
| 4 | WARL (0x0) | **S**. Hardwired to 0. |
+-------+-------------+----------------------------------------------------------------+
| 3 | WARL (0x0) | **U**. Hardwired to 0. |
| 3 | WARL (0x0) | **U**. Hardwired to 0. |
+-------+-------------+----------------------------------------------------------------+
| 2 | WARL | **EXECUTE**. Enable matching on instruction address. |
+-------+-------------+----------------------------------------------------------------+
Expand Down Expand Up @@ -1637,8 +1636,8 @@ Detailed:
+=======+============+==================================================================+
| 31:16 | WARL (0x0) | Hardwired to 0. |
+-------+------------+------------------------------------------------------------------+
| 15:0 | R (0x20, | **INFO**. Type 5 and 6 is supported. |
| | 0x40) | |
| 15:0 | R (0x20, | **INFO**. Type 5 and 6 are supported. |
| | 0x40) | |
+-------+------------+------------------------------------------------------------------+

The **info** field contains one bit for each possible `type` enumerated in
Expand Down Expand Up @@ -1697,23 +1696,23 @@ Detailed:
+----------+--------------+-------------------------------------------------------------------------------------------------+
| Bit # | R/W | Description |
+==========+==============+=================================================================================================+
| 31:28 | R (0x4) | **XDEBUGVER**. returns 4 - External debug support exists as it is described in [RISC-V-DEBUG]_. |
| 31:28 | R (0x4) | **XDEBUGVER**. External debug support exists as described in [RISC-V-DEBUG]_. |
+----------+--------------+-------------------------------------------------------------------------------------------------+
| 27:18 | WARL (0x0) | Reserved |
+----------+--------------+-------------------------------------------------------------------------------------------------+
| 17 | WARL (0x0) | **EBREAKVS**. Hardwired to 0 |
+----------+--------------+-------------------------------------------------------------------------------------------------+
| 16 | WARL (0x0) | **EBREAKVU**. Hardwired to 0. |
+----------+--------------+-------------------------------------------------------------------------------------------------+
| 15 | RW | **EBREAKM**. Set to enter debug mode on ebreak. |
| 15 | RW | **EBREAKM**. Set to enter debug mode on ``ebreak`` during machine mode. |
+----------+--------------+-------------------------------------------------------------------------------------------------+
| 14 | WARL (0x0) | Hardwired to 0. |
+----------+--------------+-------------------------------------------------------------------------------------------------+
| 13 | WARL (0x0) | **EBREAKS**. Hardwired to 0. |
+----------+--------------+-------------------------------------------------------------------------------------------------+
| 12 | WARL (0x0) | **EBREAKU**. Hardwired to 0. |
+----------+--------------+-------------------------------------------------------------------------------------------------+
| 11 | WARL | **STEPIE**: Set to enable interrupts during single stepping. |
| 11 | WARL | **STEPIE**. Set to enable interrupts during single stepping. |
+----------+--------------+-------------------------------------------------------------------------------------------------+
| 10 | WARL (0x0) | **STOPCOUNT**. Hardwired to 0. |
+----------+--------------+-------------------------------------------------------------------------------------------------+
Expand All @@ -1729,7 +1728,7 @@ Detailed:
+----------+--------------+-------------------------------------------------------------------------------------------------+
| 2 | RW | **STEP**. Set to enable single stepping. |
+----------+--------------+-------------------------------------------------------------------------------------------------+
| 1:0 | WARL (0x3) | **PRV**. Returns the priviledge mode before debug entry. |
| 1:0 | WARL (0x3) | **PRV**. Returns the privilege mode before debug entry. |
+----------+--------------+-------------------------------------------------------------------------------------------------+

.. _csr-dpc:
Expand Down