Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Fix mstatush_n for RVFI hookup #595

Merged
merged 1 commit into from
Jun 27, 2022
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
14 changes: 7 additions & 7 deletions rtl/cv32e40x_cs_registers.sv
Original file line number Diff line number Diff line change
Expand Up @@ -540,16 +540,16 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
always_comb
begin

jvt_n = {csr_wdata_int[31:10], 10'b0000000000};
jvt_n = csr_wdata_int & CSR_JVT_MASK;
jvt_we = 1'b0;

mscratch_n = csr_wdata_int;
mscratch_we = 1'b0;

mepc_n = csr_wdata_int & ~32'b1;
mepc_n = csr_wdata_int & CSR_MEPC_MASK;
mepc_we = 1'b0;

dpc_n = csr_wdata_int & ~32'b1;
dpc_n = csr_wdata_int & CSR_DPC_MASK;
dpc_we = 1'b0;

dcsr_n = '{
Expand Down Expand Up @@ -616,7 +616,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
};
mstatus_we = 1'b0;

mstatush_n = csr_wdata_int;
mstatush_n = mstatush_rdata; // Read only
mstatush_we = 1'b0;

misa_n = misa_rdata; // Read only
Expand All @@ -637,13 +637,13 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
mintstatus_n = mintstatus_rdata; // Read only
mintstatus_we = 1'b0;

mintthresh_n = {24'h000000, csr_wdata_int[7:0]};
mintthresh_n = csr_wdata_int & CSR_MINTTHRESH_MASK;
mintthresh_we = 1'b0;

mscratchcsw_n = csr_wdata_int;
mscratchcsw_n = csr_wdata_int; // todo: isssue 589
mscratchcsw_we = 1'b0;

mscratchcswl_n = csr_wdata_int;
mscratchcswl_n = csr_wdata_int; // todo: isssue 589
mscratchcswl_we = 1'b0;

mie_n = '0;
Expand Down
6 changes: 6 additions & 0 deletions rtl/include/cv32e40x_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -424,6 +424,12 @@ typedef enum logic[11:0] {
CSR_MCONFIGPTR = 12'hF15
} csr_num_e;

// CSR Bit Implementation Masks
parameter CSR_JVT_MASK = 32'hFFFFFC00;
parameter CSR_MEPC_MASK = 32'hFFFFFFFE;
parameter CSR_DPC_MASK = 32'hFFFFFFFE;
parameter CSR_MINTTHRESH_MASK = 32'h000000FF;

// CSR operations

parameter CSR_OP_WIDTH = 2;
Expand Down