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Updated version of Zc* to v1.0.0-RC5.6 (and therefore also removed Zc… #670

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Sep 28, 2022
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Updated version of Zc* to v1.0.0-RC5.6 (and therefore also removed Zc… #670

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18 changes: 8 additions & 10 deletions docs/user_manual/source/intro.rst
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Expand Up @@ -48,9 +48,11 @@ It follows these specifications:
.. [RISC-V-ZBA_ZBB_ZBC_ZBS] RISC-V Bit Manipulation ISA-extensions, Version 1.0.0-38-g865e7a7, 2021-06-28,
https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf

.. [RISC-V-ZCA_ZCB_ZCMB_ZCMP_ZCMT] RISC-V Standard Extension for the **Zca**, **Zcb**, **Zcmb**, **Zcmp**, **Zcmt** subsets of **Zc**, v0.70.5 (not ratified yet),
.. [RISC-V-ZCA_ZCB_ZCMP_ZCMT] RISC-V Standard Extension for the **Zca**, **Zcb**, **Zcmp**, **Zcmt** subsets of **Zc**, v1.0.0-RC5.6 (not ratified yet),
https://github.com/riscv/riscv-code-size-reduction/blob/cd13c6b17ccb7e1b8fc8b69e76179b339bcc2b32/Zc-specification/Zc.adoc

https://github.com/riscv/riscv-code-size-reduction/releases/download/v1.0.0-RC5.6/Zc-v1.0.0-RC5.6.pdf

.. [RISC-V-CRYPTO] RISC-V Cryptography Extensions Volume I, Scalar & Entropy Source Instructions, Version v1.0.0, 2'nd December, 2021: Ratified,
https://github.com/riscv/riscv-crypto/releases/download/v1.0.0-scalar/riscv-crypto-spec-scalar-v1.0.0.pdf

Expand Down Expand Up @@ -83,7 +85,7 @@ Many features in the RISC-V specification are optional, and |corev| can be param
- 1.9 (not ratified yet)
- optionally enabled with the ``RV32`` parameter

In addition, the following standard instruction set extensions are available from [RISC-V-UNPRIV]_, [RISC-V-ZBA_ZBB_ZBC_ZBS]_, [RISC-V-CRYPTO]_ and [RISC-V-ZCA_ZCB_ZCMB_ZCMP_ZCMT]_.
In addition, the following standard instruction set extensions are available from [RISC-V-UNPRIV]_, [RISC-V-ZBA_ZBB_ZBC_ZBS]_, [RISC-V-CRYPTO]_ and [RISC-V-ZCA_ZCB_ZCMP_ZCMT]_.

.. list-table:: |corev| Standard Instruction Set Extensions
:header-rows: 1
Expand Down Expand Up @@ -118,23 +120,19 @@ In addition, the following standard instruction set extensions are available fro
- always enabled

* - **Zca**: Subset of the standard **Zc** Code-Size Reduction extension consisting of a subset of **C** with the FP load/stores removed.
- v0.70.5 (not ratified yet; version will change)
- v1.0.0-RC5.6 (not ratified yet; version will change)
- always enabled

* - **Zcb**: Subset of the standard **Zc** Code-Size Reduction extension consisting of simple operations.
- v0.70.5 (not ratified yet; version will change)
- always enabled

* - **Zcmb**: Subset of the standard **Zc** Code-Size Reduction extension consisting of load/store byte/half which overlap with **c.fld**, **c.fldsp**, **c.fsd**.
- v0.70.5 (not ratified yet; version will change)
- v1.0.0-RC5.6 (not ratified yet; version will change)
- always enabled

* - **Zcmp**: Subset of the standard **Zc** Code-Size Reduction extension consisting of push/pop and double move which overlap with **c.fsdsp**.
- v0.70.5 (not ratified yet; version will change)
- v1.0.0-RC5.6 (not ratified yet; version will change)
- always enabled

* - **Zcmt**: Subset of the standard **Zc** Code-Size Reduction extension consisting of table jump.
- v0.70.5 (not ratified yet; version will change)
- v1.0.0-RC5.6 (not ratified yet; version will change)
- always enabled

* - **A**: Atomic Instructions
Expand Down
2 changes: 1 addition & 1 deletion docs/user_manual/source/pma.rst
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Expand Up @@ -42,7 +42,7 @@ Modifiable/modified transactions are not supported in I/O regions. An attempt t
load access fault (exception code 5). An attempt to perform a modifiable/modified store access to an I/O region causes a precise store access fault (exception code 7).

.. note::
The [RISC-V-ZCA_ZCB_ZCMB_ZCMP_ZCMT]_ specification leaves it to the core implementation whether ``cm.push``, ``cm.pop``, ``cm.popret`` and ``cm.popretz`` instructions
The [RISC-V-ZCA_ZCB_ZCMP_ZCMT]_ specification leaves it to the core implementation whether ``cm.push``, ``cm.pop``, ``cm.popret`` and ``cm.popretz`` instructions
are supported to non-idempotent memories or not. In |corev| the ``cm.push``, ``cm.pop``, ``cm.popret`` and ``cm.popretz`` instructions
are **not** allowed to perform their load or store acceses to non-idempotent memories (I/O) and a load access fault (exception code 5) or store access fault (exception code 7)
will occur upon the first such load or store access violating this requirement (meaning that the related ``pop`` or ``push`` might become partially executed).
Expand Down