Updated to latest RISC-V Debug specification. Added support for disab…

README.md

@@ -5,7 +5,7 @@ CV32E40X is a small and efficient, 32-bit, in-order RISC-V core with a 4-stage p
 * RV32[I|E]
 * [A]
 * [M|Zmmul]
-* Zca_Zcb_Zcmb_Zcmp_Zcmt
+* Zca_Zcb_Zcmp_Zcmt
 * [Zba_Zbb_Zbs|Zba_Zbb_Zbc_Zbs]
 * Zicntr
 * Zihpm

docs/user_manual/source/control_status_registers.rst

@@ -1455,7 +1455,7 @@ Reset Value: 0x0000_0000
 .. _csr-tdata1:
 
 Trigger Data 1 (``tdata1``)
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 CSR Address: 0x7A1
 
@@ -1468,24 +1468,24 @@ Reset Value: 0x6800_1000
   +-------+-------------+----------------------------------------------------------------+
   | Bit#  | R/W         | Description                                                    |
   +=======+=============+================================================================+
-  | 31:28 | WARL (0x5,  | **TYPE**. 5 = Exception trigger, 6 = Address match trigger     |
-  |       | 0x6)        | type.                                                          |
+  | 31:28 | WARL (0x5,  | **TYPE**. 0x5 (``etrigger``), 0x6 (``mcontrol6``),             |
+  |       | 0x6, 0xF)   | 0xF (``disabled``).                                            |
   +-------+-------------+----------------------------------------------------------------+
   | 27    | WARL (0x1)  | **DMODE**. Only debug mode can write ``tdata`` registers.      |
   +-------+-------------+----------------------------------------------------------------+
   | 26:0  | WARL        | **DATA**. Trigger data depending on type                       |
   +-------+-------------+----------------------------------------------------------------+
 
 .. note::
-   The WARL behavior of ``tdata1.DATA`` depends on the value of ``tdata1.TYPE`` as described for
-   ``mcontrol6`` and ``etrigger``.
+   The WARL behavior of ``tdata1.DATA`` depends on the value of ``tdata1.TYPE`` as described in
+   :ref:`csr-mcontrol6`, :ref:`csr-etrigger` and :ref:`csr-tdata1_disabled`.
 
 .. _csr-mcontrol6:
 
 Match Control Type 6 (``mcontrol6``)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-CSR Address: 0x7A1 (``mcontrol6`` is accessible as ``tdata1`` when ``tdata1.TYPE`` is 6)
+CSR Address: 0x7A1 (``mcontrol6`` is accessible as ``tdata1`` when ``tdata1.TYPE`` is 0x6)
 
 Reset Value: Not applicable
 
@@ -1542,7 +1542,7 @@ Reset Value: Not applicable
 Exception Trigger (``etrigger``)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-CSR Address: 0x7A1 (``etrigger`` is accessible as ``tdata1`` when ``tdata1.TYPE`` is 5)
+CSR Address: 0x7A1 (``etrigger`` is accessible as ``tdata1`` when ``tdata1.TYPE`` is 0x5)
 
 Reset Value: Not applicable
 
@@ -1578,6 +1578,31 @@ Reset Value: Not applicable
   | 5:0   | WARL (0x1)   | **ACTION**. Enter debug mode on match.                         |
   +-------+--------------+----------------------------------------------------------------+
 
+.. _csr-tdata1_disabled:
+
+Trigger Data 1 (``tdata1``) - ``disabled`` view
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+CSR Address: 0x7A1 (``tdata1`` view when ``tdata1.TYPE`` is 0xF)
+
+Reset Value: Not applicable
+
+.. table::
+  :widths: 10 20 70
+  :class: no-scrollbar-table
+
+
+  +-------+-------------+----------------------------------------------------------------+
+  | Bit#  | R/W         | Description                                                    |
+  +=======+=============+================================================================+
+  | 31:28 | WARL (0xF)  | **TYPE**. 0xF (``disabled``).                                  |
+  +-------+-------------+----------------------------------------------------------------+
+  | 27    | WARL (0x1)  | **DMODE**. Only debug mode can write ``tdata`` registers.      |
+  +-------+-------------+----------------------------------------------------------------+
+  | 26:0  | WARL (0x0)  | **DATA**.                                                      |
+  +-------+-------------+----------------------------------------------------------------+
+
+
 .. _csr-tdata2:
 
 Trigger Data Register 2 (``tdata2``)
@@ -1633,7 +1658,7 @@ Trigger Info (``tinfo``)
 
 CSR Address: 0x7A4
 
-Reset Value: 0x0000_0060
+Reset Value: 0x0000_8060
 
 Detailed:
 
@@ -1646,8 +1671,7 @@ Detailed:
   +=======+============+==================================================================+
   | 31:16 | WARL (0x0) | Hardwired to 0.                                                  |
   +-------+------------+------------------------------------------------------------------+
-  | 15:0  | R (0x20,   | **INFO**. Type 5 and 6 are supported.                            |
-  |       | 0x40)      |                                                                  |
+  | 15:0  | R (0x8060) | **INFO**. Types 0x5, 0x6 and 0xF are supported.                  |
   +-------+------------+------------------------------------------------------------------+
 
 The **info** field contains one bit for each possible `type` enumerated in

docs/user_manual/source/intro.rst

@@ -39,8 +39,8 @@ It follows these specifications:
 .. [RISC-V-PRIV] RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document Version 20211105-signoff (November 5, 2021),
    https://github.com/riscv/riscv-isa-manual/releases/download/draft-20211105-c30284b/riscv-privileged.pdf
 
-.. [RISC-V-DEBUG] RISC-V Debug Support, version 1.0.0-STABLE, fe3d1e65efed4b56574c50867830c3c499f9b18c,
-   https://github.com/riscv/riscv-debug-spec/blob/b659d7dc7f578e1a2a76f9e62a5eec0f2d80045c/riscv-debug-stable.pdf
+.. [RISC-V-DEBUG] RISC-V Debug Support, version 1.0.0-STABLE, 9dc1ee4e4653730f1b318731f9ea8e97f116670a,
+   https://github.com/riscv/riscv-debug-spec/blob/14a8d628e1fb736043eb54e0596adddb9717f0de/riscv-debug-stable.pdf
 
 .. [RISC-V-SMCLIC] "Smclic" Core-Local Interrupt Controller (CLIC) RISC-V Privileged Architecture Extension, version 0.9-draft, 3/15/2022,
    https://github.com/riscv/riscv-fast-interrupt/blob/af247be97888f759c61a00800f86171f28151820/clic.pdf 
@@ -187,14 +187,19 @@ The following custom instruction set extensions are available.
    can be supported by interfacing the |corev| to an external FPU via the eXtension interface.
 
 Most content of the RISC-V privileged specification is optional.
-|corev| currently supports the following features according to the RISC-V Privileged Specification [RISC-V-PRIV]_.
+|corev| supports the following features according to the RISC-V Privileged Specification [RISC-V-PRIV]_:
 
 * M-Mode
 * All CSRs listed in :ref:`cs-registers`
 * Base Counters, Timers and Hardware Performance Counters as described in :ref:`performance-counters` controlled by the ``NUM_MHPMCOUNTERS`` parameter
 * Trap handling supporting direct mode or vectored mode as described at :ref:`exceptions-interrupts`
 * Physical Memory Attribution (PMA) as described in :ref:`pma`
 
+|corev| supports the following ISA extensions from the RISC-V Debug Support specification [RISC-V-DEBUG]_:
+
+* **Sdext**: External Debug support. Always enabled.
+* **Sdtrig**: Trigger Module. Optionally enabled with the ``DBG_NUM_TRIGGERS`` parameter.
+
 Synthesis guidelines
 --------------------