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CSR stall on CLIC pointers writing to mcause.minhv #694

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1 change: 1 addition & 0 deletions bhv/cv32e40x_wrapper.sv
Original file line number Diff line number Diff line change
Expand Up @@ -221,6 +221,7 @@ module cv32e40x_wrapper
.prefetch_valid_if_i (core_i.if_stage_i.prefetch_valid),
.prefetch_is_tbljmp_ptr_if_i (core_i.if_stage_i.prefetch_is_tbljmp_ptr),
.lsu_trans_valid_i (core_i.load_store_unit_i.trans_valid),
.csr_en_id_i (core_i.id_stage_i.csr_en),
.*);
bind cv32e40x_cs_registers:
core_i.cs_registers_i
Expand Down
6 changes: 3 additions & 3 deletions rtl/cv32e40x_controller_bypass.sv
Original file line number Diff line number Diff line change
Expand Up @@ -131,10 +131,10 @@ module cv32e40x_controller_bypass import cv32e40x_pkg::*;
// todo:low:Above loop reasoning only applies to halt_id; for other pipeline stages a local instr_valid signal can maybe be used.

// Detect when a CSR insn in in EX or WB
// mret and dret implicitly writes to CSR. (dret is killing IF/ID/EX once it is in WB and can be disregarded here.
// mret, dret and CLIC pointers implicitly writes to CSR. (dret is killing IF/ID/EX once it is in WB and can be disregarded here.
assign csr_write_in_ex_wb = (
(id_ex_pipe_i.instr_valid && (id_ex_pipe_i.csr_en || (id_ex_pipe_i.sys_en && id_ex_pipe_i.sys_mret_insn))) ||
(ex_wb_pipe_i.instr_valid && (ex_wb_pipe_i.csr_en || (ex_wb_pipe_i.sys_en && ex_wb_pipe_i.sys_mret_insn)))
(id_ex_pipe_i.instr_valid && (id_ex_pipe_i.csr_en || (id_ex_pipe_i.sys_en && id_ex_pipe_i.sys_mret_insn) || id_ex_pipe_i.instr_meta.clic_ptr)) ||
(ex_wb_pipe_i.instr_valid && (ex_wb_pipe_i.csr_en || (ex_wb_pipe_i.sys_en && ex_wb_pipe_i.sys_mret_insn) || ex_wb_pipe_i.instr_meta.clic_ptr))
);

// Stall ID when WFI or WFE is active in EX.
Expand Down
13 changes: 12 additions & 1 deletion sva/cv32e40x_controller_fsm_sva.sv
Original file line number Diff line number Diff line change
Expand Up @@ -97,7 +97,8 @@ module cv32e40x_controller_fsm_sva
input logic wu_wfe_i,
input logic sys_en_id_i,
input logic sys_mret_id_i,
input logic clic_ptr_in_wb
input logic clic_ptr_in_wb,
input logic csr_en_id_i
);


Expand Down Expand Up @@ -794,5 +795,15 @@ end
|->
!ctrl_fsm_o.halt_wb)
else `uvm_error("controller", "csr_restore_mret when WB is halted")

// CSR instructions should be stalled in ID if there is a CLIC pointer in EX or WB (RAW hazard)
a_csr_stall_on_ptr:
assert property (@(posedge clk) disable iff (!rst_n)
(csr_en_id_i && if_id_pipe_i.instr_valid) &&
((id_ex_pipe_i.instr_meta.clic_ptr && id_ex_pipe_i.instr_valid) ||
(ex_wb_pipe_i.instr_meta.clic_ptr && ex_wb_pipe_i.instr_valid))
|->
!id_valid_i)
else `uvm_error("controller", "CSR* not stalled in ID when CLIC pointer is in EX or WB")
endmodule