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DEBUG parameter #784

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merged 1 commit into from
Feb 15, 2023
+616 −470
Merged

DEBUG parameter #784

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3 changes: 2 additions & 1 deletion bhv/cv32e40x_rvfi.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,8 @@ module cv32e40x_rvfi
import cv32e40x_pkg::*;
import cv32e40x_rvfi_pkg::*;
#(
parameter bit SMCLIC = 0
parameter bit SMCLIC = 0,
parameter int DEBUG = 1
)
(
input logic clk_i,
Expand Down
19 changes: 14 additions & 5 deletions bhv/cv32e40x_wrapper.sv
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Expand Up @@ -71,6 +71,7 @@ module cv32e40x_wrapper
parameter int PMA_NUM_REGIONS = 0,
parameter pma_cfg_t PMA_CFG[PMA_NUM_REGIONS-1:0] = '{default:PMA_R_DEFAULT},
parameter bit CORE_LOG_ENABLE = 1,
parameter int DEBUG = 1,
parameter logic [31:0] DM_REGION_START = 32'hF0000000,
parameter logic [31:0] DM_REGION_END = 32'hF0003FFF
)
Expand Down Expand Up @@ -191,7 +192,7 @@ module cv32e40x_wrapper
);

bind cv32e40x_wb_stage:
core_i.wb_stage_i cv32e40x_wb_stage_sva wb_stage_sva
core_i.wb_stage_i cv32e40x_wb_stage_sva #(.DEBUG(DEBUG)) wb_stage_sva
(
.*
);
Expand Down Expand Up @@ -223,6 +224,7 @@ module cv32e40x_wrapper
core_i.controller_i.controller_fsm_i
cv32e40x_controller_fsm_sva
#(.X_EXT(X_EXT),
.DEBUG(DEBUG),
.SMCLIC(SMCLIC))
controller_fsm_sva (
.lsu_outstanding_cnt (core_i.load_store_unit_i.cnt_q),
Expand All @@ -246,14 +248,15 @@ module cv32e40x_wrapper
bind cv32e40x_cs_registers:
core_i.cs_registers_i
cv32e40x_cs_registers_sva
#(.SMCLIC(SMCLIC))
#(.SMCLIC(SMCLIC),
.DEBUG (DEBUG))
cs_registers_sva (.wb_valid_i (core_i.wb_valid ),
.ctrl_fsm_cs (core_i.controller_i.controller_fsm_i.ctrl_fsm_cs),
.*);


bind cv32e40x_load_store_unit:
core_i.load_store_unit_i cv32e40x_load_store_unit_sva #(.DEPTH (DEPTH)) load_store_unit_sva (
core_i.load_store_unit_i cv32e40x_load_store_unit_sva #(.DEPTH (DEPTH), .DEBUG(DEBUG)) load_store_unit_sva (
// The SVA's monitor modport can't connect to a master modport, so it is connected to the interface instance directly:
.m_c_obi_data_if(core_i.m_c_obi_data_if),
.ex_wb_pipe_i (core_i.ex_wb_pipe),
Expand Down Expand Up @@ -319,6 +322,7 @@ module cv32e40x_wrapper
bind cv32e40x_core:
core_i cv32e40x_core_sva
#(.A_EXT(A_EXT),
.DEBUG (DEBUG),
.PMA_NUM_REGIONS(PMA_NUM_REGIONS),
.SMCLIC(SMCLIC))
core_sva (// probed cs_registers signals
Expand Down Expand Up @@ -395,6 +399,7 @@ endgenerate
.IS_INSTR_SIDE (1),
.CORE_RESP_TYPE (cv32e40x_pkg::inst_resp_t),
.CORE_REQ_TYPE (cv32e40x_pkg::obi_inst_req_t),
.DEBUG (DEBUG),
.DM_REGION_START (DM_REGION_START),
.DM_REGION_END (DM_REGION_END))
mpu_if_sva(.pma_addr (pma_i.trans_addr_i),
Expand All @@ -420,6 +425,7 @@ endgenerate
.CORE_RESP_TYPE (cv32e40x_pkg::data_resp_t),
.CORE_REQ_TYPE (cv32e40x_pkg::obi_data_req_t),
.A_EXT (A_EXT),
.DEBUG (DEBUG),
.DM_REGION_START (DM_REGION_START),
.DM_REGION_END (DM_REGION_END))
mpu_lsu_sva(.pma_addr (pma_i.trans_addr_i),
Expand Down Expand Up @@ -463,7 +469,8 @@ endgenerate
bind cv32e40x_rvfi:
rvfi_i
cv32e40x_rvfi_sva
#(.SMCLIC(SMCLIC))
#(.SMCLIC(SMCLIC),
.DEBUG (DEBUG))
rvfi_sva(.irq_ack(core_i.irq_ack),
.dbg_ack(core_i.dbg_ack),
.ebreak_in_wb_i(core_i.controller_i.controller_fsm_i.ebreak_in_wb),
Expand All @@ -488,7 +495,8 @@ endgenerate
);

cv32e40x_rvfi
#(.SMCLIC(SMCLIC))
#(.SMCLIC(SMCLIC),
.DEBUG (DEBUG))
rvfi_i
(.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
Expand Down Expand Up @@ -769,6 +777,7 @@ endgenerate
.SMCLIC ( SMCLIC ),
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ),
.SMCLIC_INTTHRESHBITS ( SMCLIC_INTTHRESHBITS ),
.DEBUG ( DEBUG ),
.DM_REGION_START ( DM_REGION_START ),
.DM_REGION_END ( DM_REGION_END ),
.DBG_NUM_TRIGGERS ( DBG_NUM_TRIGGERS ),
Expand Down
6 changes: 4 additions & 2 deletions rtl/cv32e40x_controller.sv
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Expand Up @@ -35,7 +35,8 @@ module cv32e40x_controller import cv32e40x_pkg::*;
parameter bit A_EXT = 0,
parameter int unsigned REGFILE_NUM_READ_PORTS = 2,
parameter bit SMCLIC = 0,
parameter int SMCLIC_ID_WIDTH = 5
parameter int SMCLIC_ID_WIDTH = 5,
parameter int DEBUG = 1
)
(
input logic clk, // Gated clock
Expand Down Expand Up @@ -147,7 +148,8 @@ module cv32e40x_controller import cv32e40x_pkg::*;
#(
.X_EXT ( X_EXT ),
.SMCLIC ( SMCLIC ),
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH )
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ),
.DEBUG ( DEBUG )
)
controller_fsm_i
(
Expand Down
1 change: 1 addition & 0 deletions rtl/cv32e40x_controller_fsm.sv
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Expand Up @@ -32,6 +32,7 @@
module cv32e40x_controller_fsm import cv32e40x_pkg::*;
#(
parameter bit X_EXT = 0,
parameter int DEBUG = 1,
parameter bit SMCLIC = 0,
parameter int SMCLIC_ID_WIDTH = 5
)
Expand Down
18 changes: 16 additions & 2 deletions rtl/cv32e40x_core.sv
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Expand Up @@ -36,6 +36,7 @@ module cv32e40x_core import cv32e40x_pkg::*;
parameter bit A_EXT = 0,
parameter b_ext_e B_EXT = B_NONE,
parameter m_ext_e M_EXT = M,
parameter int DEBUG = 1,
parameter logic [31:0] DM_REGION_START = 32'hF0000000,
parameter logic [31:0] DM_REGION_END = 32'hF0003FFF,
parameter int DBG_NUM_TRIGGERS = 1,
Expand Down Expand Up @@ -183,6 +184,9 @@ module cv32e40x_core import cv32e40x_pkg::*;
ctrl_byp_t ctrl_byp;
ctrl_fsm_t ctrl_fsm;

// Gated debug_req_i signal depending on DEBUG parameter
logic debug_req_gated;

// Register File Write Back
logic rf_we_wb;
rf_addr_t rf_waddr_wb;
Expand Down Expand Up @@ -393,6 +397,9 @@ module cv32e40x_core import cv32e40x_pkg::*;
assign irq_shv = ctrl_fsm.irq_shv;
assign dbg_ack = ctrl_fsm.dbg_ack;

// Gate off the internal debug_request signal if debug support is not configured.
assign debug_req_gated = DEBUG ? debug_req_i : 1'b0;

//////////////////////////////////////////////////////////////////////////////////////////////
// ____ _ _ __ __ _ //
// / ___| | ___ ___| | __ | \/ | __ _ _ __ __ _ __ _ ___ _ __ ___ ___ _ __ | |_ //
Expand Down Expand Up @@ -452,6 +459,7 @@ module cv32e40x_core import cv32e40x_pkg::*;
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ),
.ZC_EXT ( ZC_EXT ),
.M_EXT ( M_EXT ),
.DEBUG ( DEBUG ),
.DM_REGION_START ( DM_REGION_START ),
.DM_REGION_END ( DM_REGION_END )
)
Expand Down Expand Up @@ -647,6 +655,7 @@ module cv32e40x_core import cv32e40x_pkg::*;
.PMA_NUM_REGIONS (PMA_NUM_REGIONS ),
.PMA_CFG (PMA_CFG ),
.DBG_NUM_TRIGGERS (DBG_NUM_TRIGGERS ),
.DEBUG (DEBUG ),
.DM_REGION_START (DM_REGION_START ),
.DM_REGION_END (DM_REGION_END )
)
Expand Down Expand Up @@ -715,6 +724,9 @@ module cv32e40x_core import cv32e40x_pkg::*;
////////////////////////////////////////////////////////////////////////////////////////

cv32e40x_wb_stage
#(
.DEBUG ( DEBUG )
)
wb_stage_i
(
.clk ( clk ), // Not used in RTL; only used by assertions
Expand Down Expand Up @@ -784,6 +796,7 @@ module cv32e40x_core import cv32e40x_pkg::*;
.SMCLIC ( SMCLIC ),
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ),
.SMCLIC_INTTHRESHBITS ( SMCLIC_INTTHRESHBITS ),
.DEBUG ( DEBUG ),
.DBG_NUM_TRIGGERS ( DBG_NUM_TRIGGERS ),
.NUM_MHPMCOUNTERS ( NUM_MHPMCOUNTERS ),
.MTVT_ADDR_WIDTH ( MTVT_ADDR_WIDTH )
Expand Down Expand Up @@ -878,7 +891,8 @@ module cv32e40x_core import cv32e40x_pkg::*;
.A_EXT ( A_EXT ),
.REGFILE_NUM_READ_PORTS ( REGFILE_NUM_READ_PORTS ),
.SMCLIC ( SMCLIC ),
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH )
.SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ),
.DEBUG ( DEBUG )
)
controller_i
(
Expand Down Expand Up @@ -958,7 +972,7 @@ module cv32e40x_core import cv32e40x_pkg::*;
.csr_wr_in_wb_flush_i ( csr_wr_in_wb_flush ),

// Debug signals
.debug_req_i ( debug_req_i ),
.debug_req_i ( debug_req_gated ),
.dcsr_i ( dcsr ),

// Register File read, write back and forwards
Expand Down
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