Split A_EXT parameter and added wu_wrs_i pin.

bhv/cv32e40x_wrapper.sv

@@ -52,7 +52,7 @@ module cv32e40x_wrapper
 #(
   parameter              LIB                          = 0,
   parameter rv32_e       RV32                         = RV32I,
-  parameter bit          A_EXT                        = 0,
+  parameter a_ext_e      A_EXT                        = A_NONE,
   parameter b_ext_e      B_EXT                        = B_NONE,
   parameter m_ext_e      M_EXT                        = M,
   parameter bit          X_EXT                        = 0,
@@ -137,6 +137,9 @@ module cv32e40x_wrapper
   // WFE input
   input  logic        wu_wfe_i,
 
+  // WRS input
+  input  logic        wu_wrs_i,
+
   // CLIC Interface
   input  logic                       clic_irq_i,
   input  logic [SMCLIC_ID_WIDTH-1:0] clic_irq_id_i,

rtl/cv32e40x_a_decoder.sv

@@ -27,13 +27,19 @@
 ////////////////////////////////////////////////////////////////////////////////
 
 module cv32e40x_a_decoder import cv32e40x_pkg::*;
+  #(
+      parameter a_ext_e A_EXT = A
+  )
   (
    // from IF/ID pipeline
    input logic [31:0] instr_rdata_i,
 
    output             decoder_ctrl_t decoder_ctrl_o
    );
 
+  localparam A_LRSC = (A_EXT == A) || (A_EXT == ZALRSC);
+  localparam A_AMO  = (A_EXT == A);
+
   always_comb
   begin
 
@@ -56,27 +62,43 @@ module cv32e40x_a_decoder import cv32e40x_pkg::*;
 
           unique case (instr_rdata_i[31:27])
             AMO_LR: begin
-              decoder_ctrl_o.rf_re[1]     = 1'b0;
-              decoder_ctrl_o.op_c_mux_sel = OP_C_NONE;
-              decoder_ctrl_o.lsu_we       = 1'b0;
-              if (instr_rdata_i[24:20] != 5'b00000) begin
+              if (A_LRSC) begin
+                decoder_ctrl_o.rf_re[1]     = 1'b0;
+                decoder_ctrl_o.op_c_mux_sel = OP_C_NONE;
+                decoder_ctrl_o.lsu_we       = 1'b0;
+                if (instr_rdata_i[24:20] != 5'b00000) begin
+                  decoder_ctrl_o = DECODER_CTRL_ILLEGAL_INSN;
+                end
+              end else begin
                 decoder_ctrl_o = DECODER_CTRL_ILLEGAL_INSN;
               end
             end
-            AMO_SC,
-              AMO_SWAP,
-              AMO_ADD,
-              AMO_XOR,
-              AMO_AND,
-              AMO_OR,
-              AMO_MIN,
-              AMO_MAX,
-              AMO_MINU,
-              AMO_MAXU: begin
+            AMO_SC: begin
+              if (A_LRSC) begin
                 decoder_ctrl_o.rf_re[1]     = 1'b1;             // Used for operand C
                 decoder_ctrl_o.op_c_mux_sel = OP_C_REGB_OR_FWD; // Used for write data
                 decoder_ctrl_o.lsu_we       = 1'b1;
+              end else begin
+                decoder_ctrl_o = DECODER_CTRL_ILLEGAL_INSN;
               end
+            end
+            AMO_SWAP,
+            AMO_ADD,
+            AMO_XOR,
+            AMO_AND,
+            AMO_OR,
+            AMO_MIN,
+            AMO_MAX,
+            AMO_MINU,
+            AMO_MAXU: begin
+              if (A_AMO) begin
+                decoder_ctrl_o.rf_re[1]     = 1'b1;             // Used for operand C
+                decoder_ctrl_o.op_c_mux_sel = OP_C_REGB_OR_FWD; // Used for write data
+                decoder_ctrl_o.lsu_we       = 1'b1;
+              end else begin
+                decoder_ctrl_o = DECODER_CTRL_ILLEGAL_INSN;
+              end
+            end
             default : begin
               decoder_ctrl_o = DECODER_CTRL_ILLEGAL_INSN;
             end

rtl/cv32e40x_controller.sv

@@ -32,7 +32,7 @@
 module cv32e40x_controller import cv32e40x_pkg::*;
 #(
   parameter bit          X_EXT                  = 0,
-  parameter bit          A_EXT                  = 0,
+  parameter a_ext_e      A_EXT                  = A_NONE,
   parameter int unsigned REGFILE_NUM_READ_PORTS = 2,
   parameter bit          SMCLIC                 = 0,
   parameter int          SMCLIC_ID_WIDTH        = 5,

rtl/cv32e40x_controller_bypass.sv

@@ -33,7 +33,7 @@
 module cv32e40x_controller_bypass import cv32e40x_pkg::*;
 #(
   parameter int unsigned REGFILE_NUM_READ_PORTS = 2,
-  parameter bit          A_EXT                  = 1'b0
+  parameter a_ext_e      A_EXT                  = A_NONE
 )
 (
   // From decoder
@@ -239,7 +239,7 @@ module cv32e40x_controller_bypass import cv32e40x_pkg::*;
   end
 
   generate
-    if (A_EXT) begin : atomic_stall
+    if (A_EXT != A_NONE) begin : atomic_stall
       always_comb begin
         ctrl_byp_o.atomic_stall = 1'b0;
 

rtl/cv32e40x_core.sv

@@ -33,7 +33,7 @@ module cv32e40x_core import cv32e40x_pkg::*;
 #(
   parameter                             LIB                                     = 0,
   parameter rv32_e                      RV32                                    = RV32I,
-  parameter bit                         A_EXT                                   = 0,
+  parameter a_ext_e                     A_EXT                                   = A_NONE,
   parameter b_ext_e                     B_EXT                                   = B_NONE,
   parameter m_ext_e                     M_EXT                                   = M,
   parameter int                         DEBUG                                   = 1,
@@ -113,8 +113,9 @@ module cv32e40x_core import cv32e40x_pkg::*;
   // Basic interrupt architecture
   input  logic [31:0]                   irq_i,
 
-  // Event wakeup signal
-  input  logic                          wu_wfe_i,
+  // Event wakeup signals
+  input  logic                          wu_wfe_i,   // Wait-for-event wakeup
+  input  logic                          wu_wrs_i,   // Wait-for-reservation-set wakeup
 
   // Smclic interrupt architecture
   input  logic                          clic_irq_i,

rtl/cv32e40x_cs_registers.sv

@@ -30,7 +30,7 @@
 module cv32e40x_cs_registers import cv32e40x_pkg::*;
 #(
   parameter rv32_e       RV32                 = RV32I,
-  parameter bit          A_EXT                = 0,
+  parameter a_ext_e      A_EXT                = A_NONE,
   parameter m_ext_e      M_EXT                = M,
   parameter bit          X_EXT                = 0,
   parameter logic [31:0] X_MISA               =  32'h00000000,
@@ -120,14 +120,14 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
 );
 
   localparam logic [31:0] CORE_MISA =
-    (32'(A_EXT)         <<  0) | // A - Atomic Instructions extension
-    (32'(1)             <<  2) | // C - Compressed extension
-    (32'(RV32 == RV32E) <<  4) | // E - RV32E/64E base ISA
-    (32'(RV32 == RV32I) <<  8) | // I - RV32I/64I/128I base ISA
-    (32'(M_EXT == M)    << 12) | // M - Integer Multiply/Divide extension
-    (32'(0)             << 20) | // U - User mode implemented
-    (32'(1)             << 23) | // X - Non-standard extensions present
-    (32'(MXL)           << 30);  // M-XLEN
+    (32'(A_EXT == A)      <<  0) | // A - Atomic Instructions extension
+    (32'(1)               <<  2) | // C - Compressed extension
+    (32'(RV32 == RV32E)   <<  4) | // E - RV32E/64E base ISA
+    (32'(RV32 == RV32I)   <<  8) | // I - RV32I/64I/128I base ISA
+    (32'(M_EXT == M)      << 12) | // M - Integer Multiply/Divide extension
+    (32'(0)               << 20) | // U - User mode implemented
+    (32'(1)               << 23) | // X - Non-standard extensions present
+    (32'(MXL)             << 30);  // M-XLEN
 
   localparam logic [31:0] MISA_VALUE = CORE_MISA | (X_EXT ? X_MISA : 32'h0000_0000);
 

rtl/cv32e40x_decoder.sv

@@ -29,7 +29,7 @@ module cv32e40x_decoder import cv32e40x_pkg::*;
 #(
   parameter rv32_e       RV32                   = RV32I,
   parameter int unsigned REGFILE_NUM_READ_PORTS = 2,
-  parameter bit          A_EXT                  = 0,
+  parameter a_ext_e      A_EXT                  = A_NONE,
   parameter b_ext_e      B_EXT                  = B_NONE,
   parameter m_ext_e      M_EXT                  = M,
   parameter              DEBUG_TRIGGER_EN       = 1,
@@ -163,9 +163,13 @@ module cv32e40x_decoder import cv32e40x_pkg::*;
                           decoder_i_ctrl_int;
 
   generate
-    if (A_EXT) begin: a_decoder
+    if (A_EXT != A_NONE) begin: a_decoder
       // RV32A extension decoder
-      cv32e40x_a_decoder a_decoder_i
+      cv32e40x_a_decoder
+      #(
+          .A_EXT (A_EXT)
+      )
+      a_decoder_i
       (
         .instr_rdata_i  ( instr_rdata        ),
         .decoder_ctrl_o ( decoder_a_ctrl_int )

rtl/cv32e40x_id_stage.sv

@@ -33,7 +33,7 @@
 module cv32e40x_id_stage import cv32e40x_pkg::*;
 #(
   parameter rv32_e       RV32                   = RV32I,
-  parameter bit          A_EXT                  = 0,
+  parameter a_ext_e      A_EXT                  = A_NONE,
   parameter b_ext_e      B_EXT                  = B_NONE,
   parameter m_ext_e      M_EXT                  = M,
   parameter bit          X_EXT                  = 0,

rtl/cv32e40x_if_stage.sv

@@ -29,7 +29,7 @@
 module cv32e40x_if_stage import cv32e40x_pkg::*;
 #(
   parameter rv32_e       RV32            = RV32I,
-  parameter bit          A_EXT           = 0,
+  parameter a_ext_e      A_EXT           = A_NONE,
   parameter b_ext_e      B_EXT           = B_NONE,
   parameter bit          X_EXT           = 0,
   parameter int          X_ID_WIDTH      = 4,

rtl/cv32e40x_load_store_unit.sv

@@ -27,7 +27,7 @@
 
 module cv32e40x_load_store_unit import cv32e40x_pkg::*;
 #(
-  parameter bit          A_EXT = 0,
+  parameter a_ext_e      A_EXT = A_NONE,
   parameter bit          X_EXT = 0,
   parameter int          X_ID_WIDTH = 4,
   parameter int          PMA_NUM_REGIONS = 0,
@@ -399,7 +399,7 @@ module cv32e40x_load_store_unit import cv32e40x_pkg::*;
 
   // Set rdata output and atomic type output depending on A_EXT
   generate
-    if (A_EXT) begin : a_ext
+    if (A_EXT != A_NONE) begin : a_ext
       lsu_atomic_e lsu_atomic_q;
 
       always_ff @(posedge clk, negedge rst_n)

rtl/cv32e40x_mpu.sv

@@ -25,7 +25,7 @@
 
 module cv32e40x_mpu import cv32e40x_pkg::*;
   #(  parameter bit          IF_STAGE                     = 1,
-      parameter bit          A_EXT                        = 0,
+      parameter a_ext_e      A_EXT                        = A_NONE,
       parameter type         CORE_REQ_TYPE                = obi_inst_req_t,
       parameter type         CORE_RESP_TYPE               = inst_resp_t,
       parameter type         BUS_RESP_TYPE                = obi_inst_resp_t,

rtl/cv32e40x_pma.sv

@@ -25,7 +25,7 @@
 
 module cv32e40x_pma import cv32e40x_pkg::*;
 #(
-  parameter bit          A_EXT = 0,
+  parameter a_ext_e      A_EXT = A_NONE,
   parameter int          PMA_NUM_REGIONS = 0,
   parameter pma_cfg_t    PMA_CFG[PMA_NUM_REGIONS-1:0] = '{default:PMA_R_DEFAULT}
 )

rtl/include/cv32e40x_pkg.sv

@@ -1461,6 +1461,9 @@ typedef struct packed {
   // OBI interface FSM state encoding
   typedef enum logic {TRANSPARENT, REGISTERED} obi_if_state_e;
 
+  // Enum used for configuration of A extension
+  typedef enum logic [1:0] {A_NONE, ZALRSC, A} a_ext_e;
+
   // Enum used for configuration of B extension
   typedef enum logic [1:0] {B_NONE, ZBA_ZBB, ZBA_ZBB_ZBS, ZBA_ZBB_ZBC_ZBS} b_ext_e;
 

sva/cv32e40x_core_sva.sv

@@ -26,10 +26,10 @@ module cv32e40x_core_sva
   import uvm_pkg::*;
   import cv32e40x_pkg::*;
   #(
-    parameter bit A_EXT = 0,
-    parameter int DEBUG = 1,
-    parameter int PMA_NUM_REGIONS = 0,
-    parameter bit SMCLIC = 0
+    parameter a_ext_e A_EXT = A_NONE,
+    parameter int     DEBUG = 1,
+    parameter int     PMA_NUM_REGIONS = 0,
+    parameter bit     SMCLIC = 0
   )
   (
   input logic        clk,
@@ -424,7 +424,7 @@ end
 
 
   generate
-    if (!A_EXT) begin
+    if (A_EXT == A_NONE) begin
       a_atomic_disabled_never_atop :
         assert property (@(posedge clk) disable iff (!rst_ni)
                          (data_atop_o == 6'b0) &&

sva/cv32e40x_decoder_sva.sv

@@ -27,7 +27,7 @@ module cv32e40x_decoder_sva
   import uvm_pkg::*;
   import cv32e40x_pkg::*;
 #(
-  parameter bit A_EXT     = 1'b0
+  parameter a_ext_e A_EXT     = A_NONE
 )
 (
   input logic           clk,
@@ -70,11 +70,21 @@ module cv32e40x_decoder_sva
   a_uncompressed_lsb: assert property(p_uncompressed_lsb) else `uvm_error("decoder", "2 LSBs not 2'b11")
 
   generate
-    if (!A_EXT) begin : gen_no_a_extension_assertions
+    if (A_EXT == A_NONE) begin : gen_no_a_extension_assertions
       // Check that A extension opcodes are decoded as illegal when A extension not enabled
       a_illegal_0 :
         assert property (@(posedge clk) disable iff (!rst_n)
           (instr_rdata[6:0] == OPCODE_AMO) |-> (decoder_ctrl_mux.illegal_insn == 'b1))
+        else `uvm_error("decoder", "All atomic instructions should be illegal")
+    end
+
+    if (A_EXT == ZALRSC) begin : gen_no_a_ext_amo_assertions
+      // Check that A extension AMO opcodes are decoded as illegal when A extension not enabled
+      a_illegal_0 :
+        assert property (@(posedge clk) disable iff (!rst_n)
+          (instr_rdata[6:0] == OPCODE_AMO) &&
+          (instr_rdata[31:27] inside {AMO_SWAP, AMO_ADD, AMO_XOR, AMO_AND, AMO_OR, AMO_MIN, AMO_MAX, AMO_MINU, AMO_MAXU})
+          |-> (decoder_ctrl_mux.illegal_insn == 'b1))
         else `uvm_error("decoder", "AMO instruction should be illegal")
     end
   endgenerate

sva/cv32e40x_mpu_sva.sv

@@ -29,7 +29,7 @@ module cv32e40x_mpu_sva import cv32e40x_pkg::*; import uvm_pkg::*;
       parameter int unsigned IS_INSTR_SIDE = 0,
       parameter type         CORE_RESP_TYPE = inst_resp_t,
       parameter type         CORE_REQ_TYPE  = obi_inst_req_t,
-      parameter bit          A_EXT = 1'b0,
+      parameter a_ext_e      A_EXT = A_NONE,
       parameter int          DEBUG = 1,
       parameter logic [31:0] DM_REGION_START = 32'hF0000000,
       parameter logic [31:0] DM_REGION_END   = 32'hF0003FFF)
@@ -415,7 +415,7 @@ module cv32e40x_mpu_sva import cv32e40x_pkg::*; import uvm_pkg::*;
   endgenerate
 
 
-if (A_EXT) begin
+if (A_EXT != A_NONE) begin
   if (DEBUG) begin
     // Check that PMA sets correct attribution for non-atomic accesses DM during debug
     // main, non-cacheable, non-bufferable, non-atomics