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Updated cycle counts in the pipeline chapter. #942

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Sep 11, 2023
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Updated cycle counts in the pipeline chapter. #942

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ef8a3e8
Updated cycle counts in the pipeline chapter.
silabs-oysteink Sep 8, 2023
eb0070a
Updates after review.
silabs-oysteink Sep 11, 2023
130aff8
Update pipeline.rst
Silabs-ArjanB Sep 11, 2023
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48 changes: 36 additions & 12 deletions docs/user_manual/source/pipeline.rst
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Expand Up @@ -41,12 +41,8 @@ and zero stall on the data-side memory interface.
| Integer Computational | 1 | Integer Computational Instructions are defined in the |
| | | RISCV-V RV32I Base Integer Instruction Set. |
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| CSR Access | 4 (mstatus, mepc, mtvec, mcause, | CSR Access Instruction are defined in 'Zicsr' of the |
| | mcycle, minstret, mhpmcounter*, | RISC-V specification. |
| | mcycleh, minstreth, mhpmcounter*h, | |
| | mcountinhibit, mhpmevent*, dscr, | |
| | dpc, dscratch0, dscratch1, privlv) | |
| | | |
| CSR Access | 4 (``jvt``) | CSR Access Instruction are defined in 'Zicsr' of the |
| | | RISC-V specification. |
| | 1 (all the other CSRs) | |
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| Load/Store | 1 | Load/Store is handled in 1 bus transaction using both EX |
Expand All @@ -57,9 +53,9 @@ and zero stall on the data-side memory interface.
| | 2 (halfword transfer crossing | |
| | word boundary) | |
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| Multiplication | 1 (mul) | |corev| uses a single-cycle 32-bit x 32-bit multiplier |
| Multiplication | 1 (``mul``) | |corev| uses a single-cycle 32-bit x 32-bit multiplier |
| | | with a 32-bit result. The multiplications with upper-word |
| | 4 (mulh, mulhsu, mulhu) | result take 4 cycles to compute. |
| | 4 (``mulh``, ``mulhsu``, ``mulhu``) | result take 4 cycles to compute. |
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| Division | 3 - 35 | The number of cycles depends on the divider operand value |
| | | (operand b), i.e. in the number of leading bits at 0. |
Expand Down Expand Up @@ -87,20 +83,48 @@ and zero stall on the data-side memory interface.
| | 4 (target is a non-word-aligned | EX stage and will cause a flush of the IF stage (including |
| | non-RVC instruction) | prefetch buffer) and ID stage. |
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| Instruction Fence | 5 | The FENCE.I instruction as defined in 'Zifencei' of the |
| ``fence.i`` | 5 | The ``fence.i`` instruction is defined in 'Zifencei' of the |
| | | RISC-V specification. Internally it is implemented as a |
| | 6 (target is a non-word-aligned | jump to the instruction following the fence. The jump |
| | non-RVC instruction) | performs the required flushing as described above. |
| | | A ``fence.i`` instruction will not complete until |
| | | the external handshake has been completed. |
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| ``fence`` | 5 | The ``fence`` instruction is implemented as a jump to the |
| | | instruction instruction following the fence. |
| | 6 (target is a non-word-aligned | |
| | non-RVC instruction) | |
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| Zba, Zbb, Zbc, Zbs | 1 | All instructions from Zba, Zbb, Zbc, Zbs take 1 cycle. |
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| Zcmt | 2 | Table jumps take 2 cycles. |
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| Zcmp | 2 - 18 | The number of cycles depends on the number of registers |
| | | saved or restored by the instructions. |
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| Zca, Zcb | 1 | Instructions from Zca and Zcb take 1 cycle. |
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| ``wfi``, ``wfe`` | 2 - | Instructions causing sleep will not retire until wakeup. |
+-----------------------+--------------------------------------+-------------------------------------------------------------+


Hazards
-------

The |corev| experiences a 1 cycle penalty on the following hazards.

* Load data hazard (in case the instruction immediately following a load uses the result of that load)
* Jump register (jalr) data hazard (in case that a jalr depends on the result of an immediately preceding non-load instruction)
* Load data hazard (in case the instruction immediately following a load uses the result of that load).
* Jump register (``jalr``) data hazard (in case that a ``jalr`` depends on the result of an immediately preceding non-load instruction).
* An instruction causing an implicit CSR read in ID (``mret`` or table jump) while a CSR access instruction or an instruction causing an implicit CSR access is in the WB stage.
* An instruction causing an implicit CSR read in EX while a CSR access instruction or an instruction causing an implicit CSR access is in the WB stage.
* An instruction causing an explicit CSR read in EX while an instruction causing an implicit CSR write is in the WB stage.
* An instruction causing an explicit CSR read in EX while there is a RAW hazard with an explicit CSR write in WB.

The |corev| experiences a 2 cycle penalty on the following hazards.

* Jump register (jalr) data hazard (in case that a jalr depends on the result of an immediately preceding load instruction)
* Jump register (``jalr``) data hazard (in case that a ``jalr`` depends on the result of an immediately preceding load instruction).
* An instruction causing an implicit CSR read in ID (``mret`` or table jump) while a CSR access instruction or an instruction causing an implicit CSR access is in the EX stage.

.. note::
Implicit CSR reads are reads performed by non-CSR instructions or CSR instructions reading CSR values from another CSR.
Explicit CSR reads and writes are CSR instructions accessing the CSR encoded in the instruction word.