Fix for issue openhwgroup#341.

Removed sticky debug request (debug_req_q)

Updated assertion a_fencei_hndshk_req_when_fencei_wb to accomodate changes.

Signed-off-by: Oystein Knauserud <[email protected]>

Author: silabs-oysteink

rtl/cv32e40x_controller_fsm.sv

@@ -137,9 +137,6 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*;
   // Debug state
   debug_state_e debug_fsm_cs, debug_fsm_ns;
 
-  // Sticky version of debug_req_i
-  logic debug_req_q;
-
   // Sticky version of lsu_err_wb_i
   logic nmi_pending_q;
   logic nmi_is_store_q; // 1 for store, 0 for load
@@ -482,8 +479,12 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*;
                               (ebreak_in_wb && dcsr_i.ebreakm && !debug_mode_q) || // Ebreak with dcsr.ebreakm==1
                               (ebreak_in_wb && debug_mode_q); // Ebreak during debug_mode restarts execution from dm_halt_addr, as a regular debug entry without CSR updates.
 
-  // Debug pending for external debug request
-  assign pending_async_debug = ((debug_req_i || debug_req_q) && !debug_mode_q);
+  // Debug pending for external debug request, only if not already in debug mode
+  // Ideally the !debug_mode_q below should be factored into async_debug_allowed, but
+  // that can currently cause a deadlock if debug_req_i gets asserted while in debug mode, as
+  // a pending but not allowed async debug will cause the ID stage to halt forever while trying
+  // to get to an interruptible state.
+  assign pending_async_debug = debug_req_i && !debug_mode_q;
 
   // Determine cause of debug. Set for all causes of debug entry.
   // In case of ebreak during debug mode, the entry code in DEBUG_TAKEN will
@@ -1129,18 +1130,6 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*;
   assign ctrl_fsm_o.debug_mode_if = debug_mode_n;
   assign ctrl_fsm_o.debug_mode    = debug_mode_q;
 
-  // sticky version of debug_req (must be on clk_ungated_i such that incoming pulse before core is enabled is not missed)
-  always_ff @(posedge clk_ungated_i, negedge rst_n) begin
-    if (rst_n == 1'b0) begin
-      debug_req_q <= 1'b0;
-    end else begin
-      if (debug_req_i) begin
-        debug_req_q <= 1'b1;
-      end else if (debug_mode_q) begin
-        debug_req_q <= 1'b0;
-      end
-    end
-  end
 
   // Sticky version of lsu_err_wb_i
   always_ff @(posedge clk, negedge rst_n) begin

sva/cv32e40x_controller_fsm_sva.sv

@@ -244,9 +244,10 @@ module cv32e40x_controller_fsm_sva
       else `uvm_error("controller", "Fencei request when no fencei in writeback")
 
   // Assert that the fencei request is set the cycle after fencei instruction enters WB (if fencei_ready=1 and there are no higher priority events)
+  // Only check when no higher priority event is pending (nmi, async debug or interrupts) and WB stage is not killed
   a_fencei_hndshk_req_when_fencei_wb :
     assert property (@(posedge clk) disable iff (!rst_n)
-           $rose(fencei_in_wb && fencei_ready) && !(pending_nmi || (pending_async_debug && async_debug_allowed) || (pending_interrupt && interrupt_allowed))
+           $rose(fencei_in_wb && fencei_ready) && !ctrl_fsm_o.kill_wb && !(pending_nmi || (pending_async_debug && async_debug_allowed) || (pending_interrupt && interrupt_allowed))
                      |=> $rose(fencei_flush_req_o))
       else `uvm_error("controller", "Fencei in WB did not result in fencei_flush_req_o")