Sticky version of debug request

[Silabs-ArjanB]

The debug request of the core is made sticky in two places it seems (i.e. in the debug module itself and in the core). That seems incorrect although the debug specification is quite unclear about haltreq as well (specifically where it states "this may cancel outstanding halt requests for those harts").

The following needs to be addressed:

• The 'this may' part of the debug specification needs to get clarified. For the 40X the core itself will also remember the debug request, which offers less controller to the debugger.
• Any debug entry (i.e. not only debug entry due to a debug request) will cause debug_req_q to get cleared, which seems like an issue as well (see

  cv32e40x/rtl/cv32e40x_controller_fsm.sv

  Line 742 in af71c0e

  end else if (debug_mode_q) begin

  )

[Silabs-ArjanB]

See clarifications at riscv/riscv-debug-spec#753

[Silabs-ArjanB]

Can be closed once user manual has been updated as well.