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Added missing exception codes for dealing with misaligned atomic inst… #788

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Feb 20, 2023
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Added missing exception codes for dealing with misaligned atomic inst… #788

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12 changes: 12 additions & 0 deletions docs/user_manual/source/exceptions_interrupts.rst
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Expand Up @@ -24,10 +24,14 @@ Exceptions
+----------------+----------------+---------------------------------------+---------------------------------------------------------------------------+
| 0 | 3 | Breakpoint | Environment break. |
+----------------+----------------+---------------------------------------+---------------------------------------------------------------------------+
| 0 | 4 | Load address misaligned | Non-naturally aligned Load-Reserved address. |
+----------------+----------------+---------------------------------------+---------------------------------------------------------------------------+
| 0 | 5 | Load access fault | Non-naturally aligned load access attempt to an I/O region. |
| | | | Modified load access attempt to an I/O region. |
| | | | Load-Reserved attempt to region without atomic support. |
+----------------+----------------+---------------------------------------+---------------------------------------------------------------------------+
| 0 | 6 | Store/AMO address misaligned | Non-naturally aligned Store-Conditional / AMO address. |
+----------------+----------------+---------------------------------------+---------------------------------------------------------------------------+
| 0 | 7 | Store/AMO access fault | Non-naturally aligned store access attempt to an I/O region. |
| | | | Modified store access attempt to an I/O region. |
| | | | Store-Conditional or Atomic Memory Operation (AMO) attempt |
Expand All @@ -47,6 +51,8 @@ If an instruction raises multiple exceptions, the priority, from high to low, is
* ``environment break (3)``
* ``store/AMO access fault (7)``
* ``load access fault (5)``
* ``store/AMO address misaligned (6)``
* ``load address misaligned (4)``

Exceptions in general cannot be disabled and are always active.
All exceptions are precise.
Expand All @@ -57,6 +63,12 @@ is configured as a custom |corev| instruction for specific parameter settings as
An instruction bus error leads to a precise instruction interface bus fault if an attempt is made to execute the instruction that has an associated bus error.
Similarly an instruction fetch with a failing PMA check only leads to an instruction access exception if an actual execution attempt is made for it.

.. note::

The address misaligned exceptions (exception codes 4 and 6) are only triggered when Load-Reserved, Store-Conditional or AMO instructions use non-naturally aligned addresses for their data access(es)
and the access is not blocked by a higher priority access fault from the PMA (exception codes 5 or 7).
Misaligned accesses by non-Atomic instructions are either handled by hardware (no exception) or lead to access faults from the PMA (exception code 5 or 7) as explained in :ref:` misaligned-accesses`.

Non Maskable Interrupts
-----------------------

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4 changes: 3 additions & 1 deletion docs/user_manual/source/load_store_unit.rst
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Expand Up @@ -48,10 +48,12 @@ supported.
| ``data_exokay_i`` | input | Exclusive transaction status. Only valid when ``data_rvalid_i`` is high. |
+---------------------------+-----------------+------------------------------------------------------------------------------------------------------------------------------+

.. _misaligned-accesses:

Misaligned Accesses
-------------------

Misaligned transaction are supported in hardware for Main memory regions, see :ref:`pma`. For loads and stores in Main memory where the effective
Misaligned transactions (by non-atomics instructions) are supported in hardware for Main memory regions, see :ref:`pma`. For loads and stores in Main memory where the effective
address is not naturally aligned to the referenced datatype (i.e., on a four-byte boundary for word accesses, and a two-byte boundary for halfword
accesses) the load/store is performed as two bus transactions in case that the data item crosses a word boundary. A single load/store instruction
is therefore performed as two bus transactions for the following scenarios:
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4 changes: 4 additions & 0 deletions docs/user_manual/source/rvfi.rst
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Expand Up @@ -123,10 +123,14 @@ The different trap scenarios, their expected side-effects and trap signalling ar
+------------------------------+-----------+------+-----------+-------+-----------------+-------------+------------+----------------------+------------------------------------------------------------------------------------------------------+
| Breakpoint | Exception | 1 | 1 | X | 0x03 | X | 0x0 | ``mcause``, ``mepc`` | EBREAK executed with ``dcsr.ebreakm`` = 0. |
+------------------------------+-----------+------+-----------+-------+-----------------+-------------+------------+----------------------+------------------------------------------------------------------------------------------------------+
| Load Address Misaligned | Exception | 1 | 1 | X | 0x04 | X | 0x0 | ``mcause``, ``mepc`` | Non-naturally aligned Load-Reserved address. |
+------------------------------+-----------+------+-----------+-------+-----------------+-------------+------------+----------------------+------------------------------------------------------------------------------------------------------+
| Load Access Fault | Exception | 1 | 1 | X | 0x05 | X | 0x0 | ``mcause``, ``mepc`` | Non-naturally aligned load access attempt to an I/O region. |
| | | | | | | +------------+----------------------+------------------------------------------------------------------------------------------------------+
| | | | | | | | 0x1 | ``mcause``, ``mepc`` | Load-Reserved attempt to region without atomic support. |
+------------------------------+-----------+------+-----------+-------+-----------------+-------------+------------+----------------------+------------------------------------------------------------------------------------------------------+
| Store/AMO Address Misaligned | Exception | 1 | 1 | X | 0x06 | X | 0x0 | ``mcause``, ``mepc`` | Non-naturally aligned Store-Conditional / AMO address. |
+------------------------------+-----------+------+-----------+-------+-----------------+-------------+------------+----------------------+------------------------------------------------------------------------------------------------------+
| Store/AMO Access Fault | Exception | 1 | 1 | X | 0x07 | X | 0x0 | ``mcause``, ``mepc`` | Non-naturally aligned store access attempt to an I/O region. |
| | | | | | | +------------+----------------------+------------------------------------------------------------------------------------------------------+
| | | | | | | | 0x1 | ``mcause``, ``mepc`` | SC or AMO attempt to region without atomic support. |
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